Parse error of SystemVerilog set membership operator 'inside'

[KatCe]

Hello,

morty version 0.9.0 fails with a parse error in the following code example:

// filename: inside_test.sv
module test (bit clk);
  int a,b,c;
  bit d;

    if (a inside {b, c}) begin : gen_1
      assign d = 1'b1;
    end else begin : gen_0
      assign d = 1'b0;
    end
endmodule

Tool was called with morty inside_test.sv.
Error message:

Error: parse error
   --> inside_test.sv:21:11
   |
21 |     if (a inside {b, c}) begin : gen_1
   |           ^
Error: Parse error: Some(("inside_test.sv", 403))

Another test case where we expect no parse error on the 'inside' expression is:

//   typedef enum logic [2:0] {
//     testval1  = 3'd0, 
//     testval2  = 3'd1, 
//     testval3  = 3'd2
//   } test_e;
module test#(parameter test_e a) (bit clk);
  bit d;

    if (a inside {testval1, testval2}) begin : gen_1
      assign d = 1'b1;
    end else begin : gen_0
      assign d = 1'b0;
    end

endmodule

Thank you!