A community-driven compilation of RISC-V resources and learning material. The list is dynamically updated by the community and categorized based on different contexts of the RISC-V scope, taking into account different levels of experience/knowledge, allowing anyone interested in RISC-V to discover resources (courses, software, documentation, articles) in an organized fashion.
RISC-V is an open standard Instruction Set Architecture (ISA) based on established Reduced Instruction Set Computer (RISC) principles.
👋 Want to learn about RISC-V? Check out the Beginner-Level or Intermediate-Level learning resources.
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For those with little or no knowledge of digital logic design. After studying the Digital Design book, you may jump to intermediate-level courses like RVfpga.
| Resource | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
| An Introduction to Assembly Programming with RISC-V | Prof. Edson Borin | Teaches RISC-V assembly programming concepts. | Webpage | 2024-05-03 |
| Architecture 1005: RISC-V Assembly | OpenSecurityTraining | Security-focused exploration of RISC-V ISAs and extensions. | Course Videos | 2024-15-04 |
| Computer Architecture Basics | CTU Prague - FEE (Pavel Pisa) | Course covering computer architecture basics, including CPU design and speculative execution. | Course Videos | 2024-16-04 |
| Creating a RISC-V from scratch! | Lucas Teske ( Teske's Lab ) | Learning livestream series focused on creating a RV32E that runs on FPGAs | YouTube (Portuguese) | 2024-18-10 |
| Digital Design & Computer Architecture RISC-V edition | Sarah L. Harris, David M. Harris | Covers foundational digital logic design and RISC-V processor implementation. | Amazon | 2024-10-01 |
| Hands-on RISC-V Processor Design | Rahul Behl | Dive into RISC-V processor design using SystemVerilog. | QuickSilicon | 2024-10-01 |
| learn-FPGA episode I: from blinky to RISC-V | Bruno Levy | Design an FPGA-based RISC-V softcore starting from a basic Verilog blinker. | GitHub | 2024-10-01 |
| LinuxFoundationX: Building a RISC-V CPU Core | Steve Hoover | Free course on RISC-V microarchitecture design using open-source tools. | edX Course | 2024-10-01 |
| Nand2Tetris | Noam Nisan, Shimon Schocken | Build a computer from logic gates using a hardware simulator. | Website | 2024-10-01 |
| RISC-V Assembly Introduction (Portuguese) | Gabriel G. de Brito | Focus on basics of RISC-V IM architecture with the EGG emulator. | Course Videos | 2024-04-06 |
| Step-by-step RISC-V Compiler Development | Shao-Ce SUN | Practical guide to RISC-V C compiler development. | Teaching Resources and Course Videos (Chinese) | 2024-20-03 |
| Step-by-step RISC-V OS Development | Chen Wang | Practical guide for developing RISC-V operating systems. | Teaching Resources and Course Videos (Chinese) | 2024-05-03 |
| The RISC-V Reader: An Open Architecture Atlas | David Patterson, Andrew Waterman | Introduction to the RISC-V instruction set. | RISC-V Reader | 2024-05-03 |
Advanced learning materials for learners familiar with digital logic design.
| Resource | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
| Computer Architecture: A Quantitative Approach (6th Edition) | David Patterson, John Hennessy | Explores advanced topics like instruction-level parallelism and GPU architectures, using RISC-V. | Amazon | 2024-10-01 |
| Computer Organization & Design (RISC-V Edition) | David Patterson, John Hennessy | In-depth study of RISC-V ISA and processor implementation. | Amazon | 2024-10-01 |
| Learn with SHAKTI | Shakti - RISE Lab, IITM | Tutorials on RISC-V assembly programming using the RISC-V toolchain. | Learn with Shakti | 2023-21-12 |
| learn-FPGA episode II: pipelining | Bruno Levy | Extends the basic RISC-V softcore from episode I with pipelining and performance optimizations. | GitHub | 2024-10-01 |
| LinuxFoundationX: RISC-V Toolchain and Compiler Optimization Techniques | Aditya Kumar | Develop knowledge of RISC-V toolchain internals and compiler optimizations. | edX Course | 2024-10-01 |
| RISC-V Optimization Guide | RISE Project | Actionable optimization recommendations for RISC-V software developers. | GitHub | 2024-19-02 |
| RV64GC Linker from Scratch in Go | Yang Liu, PLCT Lab | Build an RV64GC architecture linker from scratch in Go. | GitHub and Course Videos (Chinese) | 2024-24-04 |
| RVfpga (Extended): Understanding Computer Architecture | Sarah Harris, Daniel Chaver-Martinez | Updated version of the RVfpga course with FPGA and simulation tools. | RVfpga v3.0 Course Link | 2024-06-02 |
| RVfpga: Computer Architecture with an Industrial RISC-V Core | Sarah Harris, Daniel Chaver-Martinez | Hands-on learning with commercial RISC-V SoC on FPGAs. | edX Course | 2024-10-01 |
| Teaching experiences with RVfpga | ARTECS Group, Complutense University of Madrid | Demonstrates how RVfpga and the Ripes simu lator were used in two courses at UCM: Computer Organization (2nd-year course) and Integrated Systems Architecture (4th-year course). | GitHub | 2024-18-10 |
| Tutorial: RISC-V Vector Extension Demystified | Thang Tran | In-depth introduction to the RISC-V vector extension. | YouTube | 2024-10-01 |
Tools to enhance understanding or visualize the RISC-V ISA.
| Tool | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
| CREATOR | Diego Camarmas Alonso, Félix García Carballeira, Alejandro Calderón Mateos, Elías del Pozo Puñal | Didactic simulator for RISC-V assembly programs. | Website | 2023-20-12 |
| emulsiV | Guillaume Savaton | Visual simulator for a minimal 32-bit RISC processor. | Website | 2023-20-12 |
| Go RISC-V Emulator | Lucas Teske | A golang implementation of RV32I+M that can run doom | GitHub | 2024-18-10 |
| GodBolt | Matt Godbolt | Online Compiler Explorer that supports GCC/LLVM for RV64 | Website | 2024-18-10 |
| Online RISC-V Assembler | Lucas Teske | Online RISC-V Assembler using gnu-assembler in webassembly | Website , Github | 2024-18-10 |
| Piscado | GustavonMartis | RISC-V Simulator written in python during twitch live coding | Github | 2024-18-10 |
| QtRvSim | CTU Prague | RISC-V simulator with cache and pipeline visualization. | GitHub | 2023-20-12 |
| RISC-V ALE | Antonio Guimarães | RISC-V Assembly Learning Environment | Website | 2024-18-10 |
| RISC-V Instruction Encoder/Decoder | LupLab | Online tool for encoding/decoding RISC-V instructions. | Website | 2023-20-12 |
| Risco-5S | Julio Nunes Avelar | RISC-V Simulator with RV32IM implementation, built during a few days off. | Github | 2023-4-11 |
| RVV Intrinsics Viewer | dzaima | Documentation for RISC-V vector extension intrinsics. | Website | 2023-20-12 |
Explore open RISC-V implementations for hands-on learning.
| Name | Description | Access | Date Added |
|---|---|---|---|
| AUK-V-Aethia | AUK-V RV32I CPU. | Github | 2024-18-10 |
| CVA6 | The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux | Github | 2024-18-10 |
| CV32E40P | CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform. | Github | 2024-18-10 |
| DarkRISCV | Small RV32-E / I soft-core CPU optimized for FPGAs. | GitHub | 2024-18-10 |
| Grande Risco-5 | RISC-V RV32I multi-cycle processor with a 5-stage pipeline, designed for educational purposes. | Github | 2024-06-11 |
| Kronos | Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations. | Github | 2024-18-10 |
| Leaf | Leaf is a small RV32I SoC for portable applications done in VHDL and implemented both in FPGA and ASIC. | Github | 2024-23-10 |
| Maestro | A 5 stage-pipeline RV32I implementation in VHDL. | Github | 2024-18-10 |
| Mriscv | A 32-bit Microcontroller featuring a RISC-V core. | Github | 2024-18-10 |
| NEORV32 | MCU-class RISC-V soft-core CPU, customizable and extensible. | GitHub | 2024-01-11 |
| NERV | Naive Educational RISC V processor | Github | 2024-18-10 |
| NoX | Small RISC-V (RV32I) core written in SystemVerilog | GitHub | 2024-21-10 |
| Pequeno | Pipelined in-order RISC-V CPU core compliant with RV32I. | GitHub | 2023-20-12 |
| PicoRV32 | A Size-Optimized RISC-V CPU | Github | 2024-18-10 |
| ReonV | ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA. | Github | 2024-18-10 |
| Riskow | Toy RV32-E done from scratch during livestreams that runs on cheap FPGAs | Github | 2024-18-10 |
| Riscado-V | Simple RISC-V (RV32I) implementation in verilog | Github | 2024-18-10 |
| Risco-5 | Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off | Github | 2024-18-10 |
| RISC-V Steel | 32-bit RISC-V processor core (RV32I + Zicsr + Machine mode) | Github | 2024-18-10 |
| RPU | Basic RISC-V CPU implementation in VHDL. | Github | 2024-18-10 |
| RSD | RSD: RISC-V Out-of-Order Superscalar Processor | Github | 2024-18-10 |
| SERV | SERV - The SErial RISC-V CPU. | Github | 2024-18-10 |
| TinyRiscv | A very simple and easy to understand RISC-V core | Github | 2024-18-10 |
| VexRiscv | A FPGA Friendly 32 bit RISC-V CPU implementation | Github | 2024-18-10 |
| Board or Dev Kit | Company | SoC | RISC-V Core | Date Added |
|---|---|---|---|---|
| DC Roma II | DeepComputing | SpacemiT K1 | Octa-Core X60™ | 2024-31-10 |
| HiFive Premier P550 | SiFive | ESWIN EIC7700X | SiFive Quad-Core P550 | 2024-31-10 |
| HiFive Unmatched | SiFive | SiFive U74‑MC | 64-bit S7 | 2024-31-10 |
| HiFive1 Rev B | SiFive | FE310-G002 | 32-bit E31 | 2024-31-10 |
| LicheeRV D1 | Sipeed | AllWinnerD1 | Single-Core T-Head C906 | 2024-31-10 |
| LicheeRV Nano | Sipeed | SG2002 | Single-Core T-HEAD C906 | 2024-31-10 |
| LicheePi 4A | Sipeed | TH1520 | Quad-Core T-HEAD C910 | 2024-31-10 |
| LicheeBook 4A | Sipeed | TH1520 | Quad-Core T-HEAD C910 | 2024-31-10 |
| LicheePi Console 4A | Sipeed | TH1520 | Quad-Core T-HEAD C910 | 2024-31-10 |
| LicheePi 3A | Sipeed | SpacemiT K1 | Octa-Core X60 | 2024-31-10 |
| VisionFive 2 | StarFiveTech | JH7110 | Quad-Core Sifive u74 | 2024-31-10 |
| Milk-V Duo | Milk-V | SG2002 | T-HEAD C906 | 2024-31-10 |
| Milk-V Mars | Milk-V | JH7110 | Quad-Core Sifive u74 | 2024-31-10 |
| Milk-V Meles | Milk-V | TH1520 | Quad-Core T-HEAD C910 | 2024-31-10 |
| Milk-V Pioneer | Milk-V | SG2042 | 64 Cores T-HEAD C910 | 2024-31-10 |
| Milk-V Vega | Milk-V | FSL1030M | UX608 Core | 2024-31-10 |
| Milk-V Jupiter | Milk-V | SpacemiT K1 | Octa-Core X60 | 2024-31-10 |
| Star 64 | Pine64 | JH7110 | Quad-Core Sifive u74 | 2024-31-10 |
| PineTab-V | Pine64 | JH7110 | Quad-Core Sifive u74 | 2024-31-10 |
| Ox64 | Pine64 | BL808 | T-HEAD C906, T-HEAD E907, T-HEAD E902 | 2024-31-10 |
| OK7110-C | ForLinx | JH7110 | Quad-Core Sifive u74 | 2024-31-10 |
| Kendryte K230 | Canaan Technology | K230 | Dual-Core T-HEAD C908 | 2024-01-11 |
| SpacemiT MUSE Pi | SpacemiT | SpacemiT M1 | Octa-Core X60 | 2024-01-11 |
| Banana Pi F3 | Banana Pi | SpacemiT K1 | Octa-Core X60 | 2024-01-11 |
| Document | Description | Access |
|---|---|---|
| Getting Started Guide | Overview of RISC-V technical organizations for new members | Google Doc |
| Member Benefits Deck | Familiarize with RISC-V member benefits and community scope | Google Doc |
| RISC-V Lifecycle Guide | Guide for RISC-V members participating in specification writing and open-source contributions | Google Doc |
| RISC-V Repository Map | Central directory of RISC-V-related repositories | GitHub Repo Map |
| RISC-V Technical Wiki | Central point for technical information related to RISC-V | Wiki |
| Resource | Author(s) | Description | Access |
|---|---|---|---|
| Design of the RISC-V Instruction Set Architecture | Andrew Waterman | PhD dissertation on the structure of the RISC-V ISA. | |
| Past, Present and Future of RISC-V | Krste Asanović | Overview of RISC-V’s evolution | YouTube |
| Is RISC-V the Future? | Roddy Urquhart | Examination of RISC-V’s future potential | Article |