From 915d0cf312f9b70228e754ec9b41baca05e30857 Mon Sep 17 00:00:00 2001 From: Ravi Sahita Date: Sun, 27 Oct 2024 22:56:54 -0700 Subject: [PATCH 1/3] added ref to normative MTT section from non-normative overview Signed-off-by: Ravi Sahita --- intro.adoc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/intro.adoc b/intro.adoc index d92abd8..6762b4f 100644 --- a/intro.adoc +++ b/intro.adoc @@ -107,9 +107,10 @@ supervisor domain may be static (e.g. device assignment to a VM) or dynamic (e.g. scheduling a VM virtual cpu within a domain). The MTT for the supervisor domain active on the hart is programmed on the hart along with the supervisor domain identifier. The MTT does not perform any address translation; it simply -provides access permissions for the physically addressed region/page (post any -S-mode and/or G-stage address translation) to enforce the isolation properties -per the use case requirements (see <>). +provides access permissions for the physically addressed regions/pages +to enforce the isolation properties per the use case requirements (see +<> for a high-level illustration and section <> for +normative details). [caption="Figure {counter:image}: ", reftext="Figure {image}"] [title= "MTT lookup for Supervisor Domain Access", id=mtt-lookup] From b9171d99fa12ba7e3c63b1850679c4b3c50d1e25 Mon Sep 17 00:00:00 2001 From: Ravi Sahita Date: Sun, 27 Oct 2024 23:05:29 -0700 Subject: [PATCH 2/3] encoding clarification for MTT implicit accesses Signed-off-by: Ravi Sahita --- chapter4.adoc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/chapter4.adoc b/chapter4.adoc index 8e87adb..3682e6b 100644 --- a/chapter4.adoc +++ b/chapter4.adoc @@ -291,6 +291,8 @@ exception corresponding to the original access type. All implicit accesses to the memory tracking table data structures in this algorithm are performed using width MTT_PTE_SIZE. +Implicit accesses to the MTT are governed by `mstatus.MBE` control for RV64 +(`mstatush.MBE` control for RV32). [NOTE] ==== From b9026b38d45a5fcf01a130c7ef39ff63726cc120 Mon Sep 17 00:00:00 2001 From: Ravi Sahita Date: Mon, 28 Oct 2024 10:31:55 -0700 Subject: [PATCH 3/3] moved location of note on MBE control Signed-off-by: Ravi Sahita --- chapter4.adoc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/chapter4.adoc b/chapter4.adoc index 3682e6b..e7358bc 100644 --- a/chapter4.adoc +++ b/chapter4.adoc @@ -291,8 +291,6 @@ exception corresponding to the original access type. All implicit accesses to the memory tracking table data structures in this algorithm are performed using width MTT_PTE_SIZE. -Implicit accesses to the MTT are governed by `mstatus.MBE` control for RV64 -(`mstatush.MBE` control for RV32). [NOTE] ==== @@ -326,7 +324,8 @@ translation, but excluding MTT checker accesses to MTT structures. Data accesses in M-mode when the MPRV bit in mstatus is set and the MPP field in mstatus contains S or U are subject to MTT checks. MTT checker accesses to MTT structures are to be treated as implicit M-mode accesses and are subject to PMP/Smepmp and -IOPMP checks. The MTT checker indexes the MTT using the +IOPMP checks. Implicit accesses to the MTT are governed by `mstatus.MBE` control +for RV64 and `mstatush.MBE` control for RV32. The MTT checker indexes the MTT using the physical address of the access to lookup and enforce the access permissions. A mismatch of the access type and the access permissions specified in the MTT entry that applies to the accessed region is reported as a trap to the