From 301469b21569d53b19ee34ab5aea375ea936bac2 Mon Sep 17 00:00:00 2001
From: rmsyn <github@weathered-steel.dev>
Date: Thu, 31 Oct 2024 03:51:06 +0000
Subject: [PATCH] riscv: add mideleg unit tests

Adds basic unit tests for the `mideleg` register.
---
 riscv/CHANGELOG.md            |  1 +
 riscv/src/register/mideleg.rs | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index e43a01ad..cf1f9a39 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -17,6 +17,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Re-use `try_*` functions in `mcountinhibit`
 - Use CSR helper macros to define `mcause` register
 - Use CSR helper macros to define `medeleg` register
+- Use CSR helper macros to define `mideleg` register
 
 ## [v0.12.1] - 2024-10-20
 
diff --git a/riscv/src/register/mideleg.rs b/riscv/src/register/mideleg.rs
index 4fb49cfb..183296a0 100644
--- a/riscv/src/register/mideleg.rs
+++ b/riscv/src/register/mideleg.rs
@@ -36,3 +36,17 @@ set_clear_csr!(
 set_clear_csr!(
     /// Supervisor External Interrupt Delegate
     , set_sext, clear_sext, 1 << 9);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mideleg() {
+        let mut m = Mideleg::from_bits(0);
+
+        test_csr_field!(m, ssoft);
+        test_csr_field!(m, stimer);
+        test_csr_field!(m, sext);
+    }
+}