diff --git a/conda-recipe/meta.yaml b/conda-recipe/meta.yaml index 95f987a..5223fd1 100644 --- a/conda-recipe/meta.yaml +++ b/conda-recipe/meta.yaml @@ -1,4 +1,4 @@ -package: +package: name: lcls2_pgp_fw_lib version: {{ GIT_DESCRIBE_TAG }} diff --git a/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Hsio.vhd b/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Hsio.vhd index f708d08..f9cb0f5 100644 --- a/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Hsio.vhd +++ b/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Hsio.vhd @@ -243,6 +243,7 @@ begin -- Trigger Interface trigger => remoteTriggers(i), triggerCode => triggerCodes(i), + triggerPause => eventTrigMsgCtrl(0).pause, -- QPLL Interface qpllLock => qpllLock(i), qpllClk => qpllClk(i), @@ -280,6 +281,7 @@ begin -- Trigger Interface trigger => remoteTriggers(i), triggerCode => triggerCodes(i), + triggerPause => eventTrigMsgCtrl(0).pause, -- PGP Serial Ports pgpRxP => qsfp0RxP(i), pgpRxN => qsfp0RxN(i), @@ -323,7 +325,7 @@ begin U_TimingRx : entity lcls2_pgp_fw_lib.TimingRx generic map ( TPD_G => TPD_G, - USE_GT_REFCLK_G => true, -- TRUE: refClkP/N + USE_GT_REFCLK_G => true, -- TRUE: refClkP/N SIMULATION_G => ROGUE_SIM_EN_G, DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G, AXIL_CLK_FREQ_G => AXIL_CLK_FREQ_G, diff --git a/hardware/XilinxKcu1500/rtl/Kcu1500Hsio.vhd b/hardware/XilinxKcu1500/rtl/Kcu1500Hsio.vhd index 1c80581..d5ce394 100644 --- a/hardware/XilinxKcu1500/rtl/Kcu1500Hsio.vhd +++ b/hardware/XilinxKcu1500/rtl/Kcu1500Hsio.vhd @@ -265,6 +265,7 @@ begin -- Trigger Interface trigger => remoteTriggers(i), triggerCode => triggerCodes(i), + triggerPause => eventTrigMsgCtrl(0).pause, -- QPLL Interface qpllLock => qpllLock(i), qpllClk => qpllClk(i), @@ -302,6 +303,7 @@ begin -- Trigger Interface trigger => remoteTriggers(i), triggerCode => triggerCodes(i), + triggerPause => eventTrigMsgCtrl(0).pause, -- PGP Serial Ports pgpRxP => qsfp0RxP(i), pgpRxN => qsfp0RxN(i), diff --git a/hardware/XilinxVariumC1100/rtl/C1100Hsio.vhd b/hardware/XilinxVariumC1100/rtl/C1100Hsio.vhd index bc3cffb..31c7c2f 100644 --- a/hardware/XilinxVariumC1100/rtl/C1100Hsio.vhd +++ b/hardware/XilinxVariumC1100/rtl/C1100Hsio.vhd @@ -254,6 +254,7 @@ begin -- Trigger Interface trigger => remoteTriggers(i), triggerCode => triggerCodes(i), + triggerPause => eventTrigMsgCtrl(0).pause, -- QPLL Interface qpllLock => qpllLock(i), qpllClk => qpllClk(i), @@ -291,6 +292,7 @@ begin -- Trigger Interface trigger => remoteTriggers(i), triggerCode => triggerCodes(i), + triggerPause => eventTrigMsgCtrl(0).pause, -- PGP Serial Ports pgpRxP => qsfp0RxP(i), pgpRxN => qsfp0RxN(i), diff --git a/shared/rtl/UltraScale+/Pgp2bLane.vhd b/shared/rtl/UltraScale+/Pgp2bLane.vhd index 1b2668a..7a97be2 100644 --- a/shared/rtl/UltraScale+/Pgp2bLane.vhd +++ b/shared/rtl/UltraScale+/Pgp2bLane.vhd @@ -39,6 +39,7 @@ entity Pgp2bLane is -- Trigger Interface trigger : in sl; triggerCode : in slv(7 downto 0) := (others => '0'); + triggerPause : in sl; -- PGP Serial Ports pgpTxP : out sl; pgpTxN : out sl; @@ -95,8 +96,20 @@ architecture mapping of Pgp2bLane is signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0); signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0); + signal triggerPauseVec : slv(7 downto 0); + begin + triggerPauseVec <= (others => triggerPause); + U_triggerPause : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 8) + port map ( + clk => pgpTxClk, + dataIn => triggerPauseVec, + dataOut => locTxIn.locData); + U_Trig : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G) diff --git a/shared/rtl/UltraScale+/Pgp4Lane.vhd b/shared/rtl/UltraScale+/Pgp4Lane.vhd index 4a481ec..ec4e197 100644 --- a/shared/rtl/UltraScale+/Pgp4Lane.vhd +++ b/shared/rtl/UltraScale+/Pgp4Lane.vhd @@ -36,7 +36,8 @@ entity Pgp4Lane is port ( -- Trigger Interface trigger : in sl; - triggerCode : in slv(7 downto 0); + triggerCode : in slv(7 downto 0) := (others => '0'); + triggerPause : in sl; -- QPLL Interface qpllLock : in slv(1 downto 0); qpllClk : in slv(1 downto 0); @@ -95,8 +96,20 @@ architecture mapping of Pgp4Lane is signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0); signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0); + signal triggerPauseVec : slv(47 downto 0); + begin + triggerPauseVec <= (others => triggerPause); + U_triggerPause : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 48) + port map ( + clk => pgpClk, + dataIn => triggerPauseVec, + dataOut => pgpTxIn.locData); + U_Trig : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G) diff --git a/shared/rtl/UltraScale/Pgp2bLane.vhd b/shared/rtl/UltraScale/Pgp2bLane.vhd index 8afb430..aaaa9f3 100644 --- a/shared/rtl/UltraScale/Pgp2bLane.vhd +++ b/shared/rtl/UltraScale/Pgp2bLane.vhd @@ -39,6 +39,7 @@ entity Pgp2bLane is -- Trigger Interface trigger : in sl; triggerCode : in slv(7 downto 0) := (others => '0'); + triggerPause : in sl; -- PGP Serial Ports pgpTxP : out sl; pgpTxN : out sl; @@ -95,8 +96,20 @@ architecture mapping of Pgp2bLane is signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0); signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0); + signal triggerPauseVec : slv(7 downto 0); + begin + triggerPauseVec <= (others => triggerPause); + U_triggerPause : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 8) + port map ( + clk => pgpTxClk, + dataIn => triggerPauseVec, + dataOut => locTxIn.locData); + U_Trig : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G) diff --git a/shared/rtl/UltraScale/Pgp4Lane.vhd b/shared/rtl/UltraScale/Pgp4Lane.vhd index 652bbb2..729bda2 100644 --- a/shared/rtl/UltraScale/Pgp4Lane.vhd +++ b/shared/rtl/UltraScale/Pgp4Lane.vhd @@ -37,7 +37,8 @@ entity Pgp4Lane is port ( -- Trigger Interface trigger : in sl; - triggerCode : in slv(7 downto 0); + triggerCode : in slv(7 downto 0) := (others => '0'); + triggerPause : in sl; -- QPLL Interface qpllLock : in slv(1 downto 0); qpllClk : in slv(1 downto 0); @@ -96,8 +97,20 @@ architecture mapping of Pgp4Lane is signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0); signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0); + signal triggerPauseVec : slv(47 downto 0); + begin + triggerPauseVec <= (others => triggerPause); + U_triggerPause : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 48) + port map ( + clk => pgpClk, + dataIn => triggerPauseVec, + dataOut => pgpTxIn.locData); + U_Trig : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G)