hang on driver

[jack4041313]

I tried to put this usb host ip into my FPGA (genesys2),
during the linux boot process, it stuck on the driver, I added some strings to the driver to find out where the machine crashed

1. First I found port_power(ue11, 0) in the probe
   
2. Found if (is_on) {....} <-- hang on here in port_power
   

Can you give me some clues?

[asyarifstudio]

hi @jack4041313 , I'm currently doing the same, trying to put this USB IP to Genesys 2 Board. do you mind to share your work. I'm not particularly good with FPGA

[jack4041313]

Hi @asyarifstudio, I didn't succeed put this IP to Genesys2, but I am willing to share my experiences. Can you give me your email?

[skiphansen]

Hi @asyarifstudio and @jack4041313 I have a different board and a different problem (#1), but perhaps we can help each other. I'm VERY interested in getting this core running.

Stupid question: have you build and loaded the Linux driver for this implementation? The readme states

This core is not compliant with any standard USB host interface specification, e.g OHCI or EHCI.

Your log seems to indicate Linux is using the standard OHCI and EHCI drivers.

Skip

[rooi-oog]

Hi, @skiphansen, here's the answer to your question - After a couple of sleepless nights, I managed to run this core under Linux. Unfortunately, there are some limitations. For example, there is no device detection/hotplugging. Therefore, the device must be connected to the host before the kernel starts the module. Another issue is that not all the full-speed devices I've connected works(specifically, composite HID devices). From my (complete newbie) point of view, this core is more of a proof-of-concept rather than ready-to-use. All experiments I've done with this board: https://github.com/xjtuecho/EBAZ4205

P.S. I've used this core as usb phy.

[skiphansen]

@rooi-oog Well you've made better progress that I have. There aren't any competing cores that I am aware of, if I can find one I'll give it a try as well. My target has a USB3300 USB PHY which eliminates a couple of other host cores that I've looked at since they drive bare FPGA pins directly. I am not knowledgeable enough the add ULPI support.

I also have a EBAZ4205, maybe I'll give it a try as well. If you don't mind sharing your project it would be helpful.

Skip

[rooi-oog]

@skiphansen Sure thing. I'm not ready to create a project on GitHub yet, but you can download all project files here. If you have any further questions, feel free to ask. My end goal is to use USB3300 as well, so I would be glad to hear if you succeeded.

P.S. If you're subscribed to the EBAZ4205 telegram channel, we could communicate there

[asyarifstudio]

Hi, I also didn't manage to make it works. I was trying to add this IP on CVA6 core. Since I was trying to integrate secure element through modem via USB, I finally ditched the USB part and connect the core directly to secure element via SPI.

[haidangvu79]

Hi @asyarifstudio, I didn't succeed put this IP to Genesys2, but I am willing to share my experiences. Can you give me your email?

Hello @jack4041313, I'm also working on the Genesys 2. Could you please share your experiences ? Thank you in advance!