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Merge pull request #2820 from verilog-to-routing/light-packing-for-logic
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Change the default output pin utilization of logic blocks to 0.6
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@vaughnbetz
vaughnbetz authored Nov 22, 2024
2 parents 920e8ab + 9ecec28 commit 3fa3148
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Showing 186 changed files with 1,009 additions and 1,018 deletions.
2 changes: 1 addition & 1 deletion vpr/src/base/vpr_types.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ t_ext_pin_util_targets::t_ext_pin_util_targets(const std::vector<std::string>& s
//input pin utilization target which is high, but less than 100%.
if (logic_block_type != nullptr) {
constexpr float LOGIC_BLOCK_TYPE_AUTO_INPUT_UTIL = 0.8;
constexpr float LOGIC_BLOCK_TYPE_AUTO_OUTPUT_UTIL = 1.0;
constexpr float LOGIC_BLOCK_TYPE_AUTO_OUTPUT_UTIL = 0.6;

t_ext_pin_util logic_block_ext_pin_util(LOGIC_BLOCK_TYPE_AUTO_INPUT_UTIL, LOGIC_BLOCK_TYPE_AUTO_OUTPUT_UTIL);

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8 changes: 4 additions & 4 deletions vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt
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@@ -1,5 +1,5 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.91 vpr 65.59 MiB -1 -1 0.21 21296 3 0.05 -1 -1 39652 -1 -1 69 99 1 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67160 99 130 353 483 1 220 299 13 13 169 clb auto 26.9 MiB 0.03 692 29270 3600 8725 16945 65.6 MiB 0.03 0.00 30 1400 11 3.33e+06 2.19e+06 408126. 2414.95 1.08
k4_N10_memSize16384_memData64.xml diffeq1.v common 4.43 vpr 69.27 MiB -1 -1 0.31 26352 23 0.22 -1 -1 41100 -1 -1 71 162 0 5 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70936 162 96 1200 1141 1 688 334 13 13 169 clb auto 30.2 MiB 0.11 5199 75604 21039 49822 4743 69.3 MiB 0.10 0.00 54 10333 34 3.33e+06 2.58e+06 696024. 4118.48 2.85
k4_N10_memSize16384_memData64.xml single_wire.v common 0.25 vpr 63.52 MiB -1 -1 0.05 19840 1 0.01 -1 -1 35512 -1 -1 0 1 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65048 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 3 1 2 0 63.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
k4_N10_memSize16384_memData64.xml single_ff.v common 0.26 vpr 63.64 MiB -1 -1 0.06 19968 1 0.01 -1 -1 35756 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65172 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 9 4 1 4 63.6 MiB 0.00 0.00 18 5 1 30000 30000 3112.78 345.864 0.01
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 2.23 vpr 62.52 MiB -1 -1 0.44 18128 3 0.11 -1 -1 33248 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64024 99 130 353 483 1 222 301 13 13 169 clb auto 22.9 MiB 0.06 730 30541 5185 13290 12066 62.5 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.60
k4_N10_memSize16384_memData64.xml diffeq1.v common 3.94 vpr 66.34 MiB -1 -1 0.54 23352 23 0.30 -1 -1 34272 -1 -1 77 162 0 5 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67928 162 96 1200 1141 1 675 340 13 13 169 clb auto 26.0 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9701 16 3.33e+06 2.76e+06 671819. 3975.26 1.21
k4_N10_memSize16384_memData64.xml single_wire.v common 0.68 vpr 60.16 MiB -1 -1 0.06 16212 1 0.03 -1 -1 29556 -1 -1 0 1 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61604 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 60.2 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
k4_N10_memSize16384_memData64.xml single_ff.v common 0.73 vpr 60.14 MiB -1 -1 0.15 16376 1 0.02 -1 -1 29780 -1 -1 1 2 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61580 2 1 3 4 1 3 4 3 3 9 -1 auto 21.3 MiB 0.00 6 9 6 0 3 60.1 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01
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