How to set IO constraints using VTR

[Sun1927]

Dear VTR team,

We are trying to set the input/output signal to specific FPGA IO port by using --read_vpr_constraints option. When writing the file, here are several questions:

1. What should be the name_pattern of <add_attom.../> tag? Can it be the name of input signal in Verilog testbench?
2. We notice in official document, it should be the name from atom netlist, but where should we find the atom netlist? Does it refer to the .net file generated after packing stage?
3. May I kindly ask an example file of IO mappings?

Thanks