Skip to content
View AnikBalo's full-sized avatar

Block or report AnikBalo

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. OpenROAD-flow-scripts OpenROAD-flow-scripts Public

    Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

    Verilog

  2. OpenLane OpenLane Public

    Forked from The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Verilog

  3. cv32e40p cv32e40p Public

    Forked from openhwgroup/cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog

  4. cva6 cva6 Public

    Forked from openhwgroup/cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    SystemVerilog

  5. cv32e40x cv32e40x Public

    Forked from openhwgroup/cv32e40x

    4 stage, in-order, compute RISC-V core based on the CV32E40P

    SystemVerilog

  6. cv32e40s cv32e40s Public

    Forked from openhwgroup/cv32e40s

    4 stage, in-order, secure RISC-V core based on the CV32E40P

    SystemVerilog