GitHub - Anish9901/verilog-simulations: Simulation of verilog projects with Icarus Verilog and GTKWave

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Simulation of verilog projects with Icarus Verilog and GTKWave

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Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
counter		counter
hello		hello
uart		uart
README.md		README.md

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How to run these files:

iverilog -o <x>.vvb <x>.v <x>.v
vvp <x>.vvb
gtkwave <x>.vcd

Simulation output of the UART protocol implemented in verilog

Screenshot 2024-11-11 at 2 53 27 AM

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Simulation of verilog projects with Icarus Verilog and GTKWave

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Verilog 100.0%