Pinned Loading

1. BrianHG-DDR3-Controller BrianHG-DDR3-Controller Public

   DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

   SystemVerilog 72 33

2. Verilog-Floating-Point-Clock-Divider Verilog-Floating-Point-Clock-Divider Public

   Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

   Verilog 14 1

3. SystemVerilog-HDMI-encoder-serializer-PLL-generator SystemVerilog-HDMI-encoder-serializer-PLL-generator Public

   SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.

   SystemVerilog 8 1

4. Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor Public

   Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.

   Verilog 9 1

5. BHG_I2C_init_RS232_debugger BHG_I2C_init_RS232_debugger Public

   A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.

   SystemVerilog 6

6. SystemVerilog-TestBench-BPM-picture-generator SystemVerilog-TestBench-BPM-picture-generator Public

   This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of yo…

   SystemVerilog 5