GitHub - ConchuOD/fpga_adpll: FPGA based ADPLL Network in Verilog - Elec&Comp Eng Masters Project 2019

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FPGA based ADPLL Network in Verilog - Elec&Comp Eng Masters Project 2019

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Name		Name	Last commit message	Last commit date
Latest commit History 250 Commits
constraints		constraints
design_sources		design_sources
matlab		matlab
sim_sources		sim_sources
waveforms		waveforms
.gitattributes		.gitattributes
.gitignore		.gitignore
LICENSE		LICENSE
Thesis.pdf		Thesis.pdf
readme.md		readme.md

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This repository contains the Verilog code from my master's project & a number of the matlab scripts used in the process of analysing measurement results.

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FPGA based ADPLL Network in Verilog - Elec&Comp Eng Masters Project 2019

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