i#3544 RV64: Preserve vtype and vl vector registers (#7110)

This patch was authored at the Computer Architecture and VLSI
Laboratory, Institute of Computer Science, Foundation of Research and
Technology, Hellas.

It emits the necessary instructions that handle saving and restoring the
vl and vtype during the context switches, when using the vector
extension of the RISC-V ISA. This is required, in order to use the
vector extension correctly.

Also corrected the order of append_restore_xflags and
append_restore_simd_reg (in emit_utils_shared.c ) in order to have the
restoration happen in the reverse order of the saving. This specific
code is not currently used for RISC-V, but it might in the future.

Issue: #3544

core/arch/arch.h

@@ -176,6 +176,8 @@ mixed_mode_enabled(void)
 #    define XFLAGS_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, fcsr)))
 #    define VSTART_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vstart)))
 #    define VCSR_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vcsr)))
+#    define VL_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vl)))
+#    define VTYPE_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vtype)))
 #    define SCRATCH_REG0 DR_REG_A0
 #    define SCRATCH_REG1 DR_REG_A1
 #    define SCRATCH_REG2 DR_REG_A2

core/arch/emit_utils_shared.c

@@ -4980,8 +4980,8 @@ emit_fcache_enter_gonative(dcontext_t *dcontext, generated_code_t *code, byte *p
     append_call_exit_dr_hook(dcontext, &ilist, absolute, shared);
 
     /* restore the original register state */
-    append_restore_xflags(dcontext, &ilist, absolute);
     append_restore_simd_reg(dcontext, &ilist, absolute);
+    append_restore_xflags(dcontext, &ilist, absolute);
     append_restore_gpr(dcontext, &ilist, absolute);
 
     /* We need to restore the stolen reg, but we have no scratch registers.

core/arch/riscv64/emit_utils.c

@@ -1,5 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2022 Rivos, Inc.  All rights reserved.
+ * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -54,6 +55,8 @@
 #define FCSR 0x003
 #define VSTART 0x008
 #define VCSR 0x00F
+#define CSR_VL 0xC20
+#define CSR_VTYPE 0xC21
 
 /* Instruction fixed bits constants. */
 
@@ -661,6 +664,12 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
             INSTR_CREATE_csrrw(dcontext, opnd_create_reg(DR_REG_ZERO),
                                opnd_create_reg(DR_REG_A0),
                                opnd_create_immed_int(VCSR, OPSZ_12b)));
+
+        APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A0, VL_OFFSET));
+        APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A1, VTYPE_OFFSET));
+        APP(ilist,
+            INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0),
+                                opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)));
     }
 }
 
@@ -877,6 +886,17 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute
                                opnd_create_reg(DR_REG_ZERO),
                                opnd_create_immed_int(VCSR, OPSZ_12b)));
         APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VCSR_OFFSET));
+
+        APP(ilist,
+            INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1),
+                               opnd_create_reg(DR_REG_ZERO),
+                               opnd_create_immed_int(CSR_VL, OPSZ_12b)));
+        APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VL_OFFSET));
+        APP(ilist,
+            INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1),
+                               opnd_create_reg(DR_REG_ZERO),
+                               opnd_create_immed_int(CSR_VTYPE, OPSZ_12b)));
+        APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET));
     }
 }
 

core/arch/riscv64/mangle.c

@@ -1,5 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2022 Rivos, Inc.  All rights reserved.
+ * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -45,6 +46,8 @@
 #define FCSR 0x003
 #define VSTART 0x008
 #define VCSR 0x00F
+#define CSR_VL 0xC20
+#define CSR_VTYPE 0xC21
 
 /* TODO i#3544: Think of a better way to represent these fields in the IR. */
 /* Volume I: RISC-V Unprivileged ISA V20191213.
@@ -192,6 +195,32 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
 
     dstack_offs += XSP_SZ;
 
+    if (proc_has_feature(FEATURE_VECTOR)) {
+        PRE(ilist, instr,
+            INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
+                               opnd_create_reg(DR_REG_ZERO),
+                               opnd_create_immed_int(CSR_VL, OPSZ_12b)));
+
+        PRE(ilist, instr,
+            INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),
+                                opnd_create_reg(DR_REG_A0)));
+    }
+
+    dstack_offs += XSP_SZ;
+
+    if (proc_has_feature(FEATURE_VECTOR)) {
+        PRE(ilist, instr,
+            INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
+                               opnd_create_reg(DR_REG_ZERO),
+                               opnd_create_immed_int(CSR_VTYPE, OPSZ_12b)));
+
+        PRE(ilist, instr,
+            INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),
+                                opnd_create_reg(DR_REG_A0)));
+    }
+
+    dstack_offs += 2 * XSP_SZ;
+
     /* Push vector registers. */
     if (proc_has_feature(FEATURE_VECTOR)) {
         /* ma:   mask agnostic
@@ -309,6 +338,25 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist
                           opnd_create_reg(DR_REG_SP),
                           opnd_create_immed_int(DR_NUM_FPR_REGS * XSP_SZ, OPSZ_12b)));
 
+    current_offs -= 2 * XSP_SZ;
+
+    /* Uses c.[f]ldsp for some reason beyond my comprehension, same below. */
+    if (proc_has_feature(FEATURE_VECTOR)) {
+        PRE(ilist, instr,
+            INSTR_CREATE_c_ldsp(
+                dcontext, opnd_create_reg(DR_REG_A0),
+                OPND_CREATE_MEM64(DR_REG_SP, current_offs - DR_NUM_FPR_REGS * XSP_SZ)));
+        PRE(ilist, instr,
+            INSTR_CREATE_c_ldsp(
+                dcontext, opnd_create_reg(DR_REG_A1),
+                OPND_CREATE_MEM64(DR_REG_SP,
+                                  current_offs + XSP_SZ - DR_NUM_FPR_REGS * XSP_SZ)));
+        /* vsetvl a0, a0, a1 */
+        PRE(ilist, instr,
+            INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0),
+                                opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)));
+    }
+
     /* Uses c.[f]ldsp to save space, same below. */
     current_offs -= XSP_SZ;
 

core/arch/riscv64/riscv64.asm

@@ -42,7 +42,7 @@ START_FILE
 
 /* sizeof(priv_mcontext_t) rounded up to a multiple of 16 */
 /* The reserved space for SIMD is also included. */
-#define PRIV_MCONTEXT_SIZE 0x620
+#define PRIV_MCONTEXT_SIZE 0x630
 
 /* offset of priv_mcontext_t in dr_mcontext_t */
 #define PRIV_MCONTEXT_OFFSET 16
@@ -52,7 +52,7 @@ START_FILE
 #endif
 
 /* offsetof(dcontext_t, dstack) */
-#define dstack_OFFSET 0x668
+#define dstack_OFFSET 0x678
 /* offsetof(dcontext_t, is_exiting) */
 #define is_exiting_OFFSET (dstack_OFFSET + 1 * ARG_SZ)
 

core/lib/mcxtx_api.h

@@ -566,6 +566,8 @@
     reg_t fcsr; /**< Floating-Point Control Register. */
     reg_t vstart; /**< Vector Start Index CSR. */
     reg_t vcsr; /**< Vector Control and Status Register. */
+    reg_t vl; /**< Vector Length Register. */
+    reg_t vtype; /**< Vector Type Register. */
     /** The Vector registers. */
     dr_simd_t simd[MCXT_NUM_SIMD_SLOTS];
 #else /* RISCV64 */