100G-verilog-RoCEv2-lite

TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

Code based on Alex Forencich code.

Name		Name	Last commit message	Last commit date
Latest commit History 31 Commits
Scripts		Scripts
sim		sim
README.md		README.md
RoCE_latency_eval.v		RoCE_latency_eval.v
RoCE_minimal_stack_512.v		RoCE_minimal_stack_512.v
RoCE_minimal_stack_64.v		RoCE_minimal_stack_64.v
RoCE_qp_state_module.v		RoCE_qp_state_module.v
RoCE_udp_rx_512.v		RoCE_udp_rx_512.v
RoCE_udp_rx_64.v		RoCE_udp_rx_64.v
RoCE_udp_tx_512.v		RoCE_udp_tx_512.v
RoCE_udp_tx_64.v		RoCE_udp_tx_64.v
Roce_tx_header_producer.v		Roce_tx_header_producer.v
axis_RoCE_icrc_insert_512.v		axis_RoCE_icrc_insert_512.v
axis_RoCE_icrc_insert_64.v		axis_RoCE_icrc_insert_64.v
axis_handshake_monitor.vhd		axis_handshake_monitor.vhd
axis_mask_fields_icrc.v		axis_mask_fields_icrc.v
udp_RoCE_connection_manager_512.v		udp_RoCE_connection_manager_512.v
udp_RoCE_connection_manager_64.v		udp_RoCE_connection_manager_64.v

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