Generate output into corresponding library directory

Instead of generating the output into a directory like "out/led/pkg/", use the actual library directory where the files need to be added to, for example "out/LibrePCB_Base.lplib/pkg". This makes it much easier to copy the generated elements into the libraries. In addition, it is less error-prone since the library assignment is now stored in the generators (currently it's cumbersome to find out which files need to be copied into which library).
LibrePCB · Aug 9, 2023 · a3b5baf · a3b5baf
1 parent 3e792ac
commit a3b5baf
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Showing 12 changed files with 83 additions and 158 deletions.
diff --git a/dfn_configs.py b/dfn_configs.py
@@ -49,6 +49,7 @@ def __init__(self,
                  lead_width: Optional[float] = None,
                  name: Optional[str] = None,
                  create_date: Optional[str] = None,
+                 library: Optional[str] = None,
                  pin1_corner_dx_dy: Optional[float] = None,  # Some parts have a triangular pin1 marking
                  extended_doc_fn: Optional[Callable[['DfnConfig', Callable[[str], str], List[str]], None]] = None,
                  ):
@@ -79,6 +80,7 @@ def __init__(self,
         self.keywords = keywords
         self.name = name
         self.create_date = create_date
+        self.library = library or "LibrePCB_Base.lplib"
 
         self.extended_doc_fn = extended_doc_fn
 
@@ -294,6 +296,7 @@ def _draw(config: DfnConfig, uuid: Callable[[str], str], lines: List[str]) -> No
         keywords='sensirion,sht,shtcx,shtc1,shtc3',
         name='SENSIRION_SHTCx',
         create_date='2019-01-24T21:50:44Z',
+        library="Sensirion.lplib",
         no_exp=False,
         pin1_corner_dx_dy=0.2,
         extended_doc_fn=draw_circle(diameter=0.9),
@@ -312,6 +315,7 @@ def _draw(config: DfnConfig, uuid: Callable[[str], str], lines: List[str]) -> No
         keywords='sensirion,sht,sht2x,sht20,sht21,sht25',
         name='SENSIRION_SHT2x',
         create_date='2019-01-24T22:13:46Z',
+        library="Sensirion.lplib",
         no_exp=False,
         pin1_corner_dx_dy=0.2,
     ),
@@ -328,6 +332,7 @@ def _draw(config: DfnConfig, uuid: Callable[[str], str], lines: List[str]) -> No
         exposed_length=1.25,
         keywords='sensirion,sgp,sgp30,sgpc3',
         name='SENSIRION_SGPxx',
+        library="Sensirion.lplib",
         no_exp=False,
         pin1_corner_dx_dy=0.3,
         extended_doc_fn=draw_circle(diameter=1.1),

diff --git a/generate_capacitor_radial_tht.py b/generate_capacitor_radial_tht.py
@@ -62,7 +62,7 @@ def get_variant(
 
 
 def generate_pkg(
-    dirpath: str,
+    library: str,
     diameter: float,
     height: float,
     pitch: float,
@@ -249,7 +249,7 @@ def _generate_fill_polygon(identifier: str, layer: str) -> Polygon:
     ))
 
     # write files
-    pkg_dir_path = path.join(dirpath, package.uuid)
+    pkg_dir_path = path.join('out', library, 'pkg', package.uuid)
     if not (path.exists(pkg_dir_path) and path.isdir(pkg_dir_path)):
         makedirs(pkg_dir_path)
     with open(path.join(pkg_dir_path, '.librepcb-pkg'), 'w') as f:
@@ -261,7 +261,7 @@ def _generate_fill_polygon(identifier: str, layer: str) -> Polygon:
 
 
 def generate_dev(
-    dirpath: str,
+    library: str,
     diameter: float,
     height: float,
     pitch: float,
@@ -306,7 +306,7 @@ def _uuid(identifier: str) -> str:
     ))
 
     # write files
-    pkg_dir_path = path.join(dirpath, device.uuid)
+    pkg_dir_path = path.join('out', library, 'dev', device.uuid)
     if not (path.exists(pkg_dir_path) and path.isdir(pkg_dir_path)):
         makedirs(pkg_dir_path)
     with open(path.join(pkg_dir_path, '.librepcb-dev'), 'w') as f:
@@ -349,7 +349,7 @@ def _uuid(identifier: str) -> str:
 
     for config in CONFIGS:
         generate_pkg(
-            dirpath='out/capacitors_radial_tht/pkg',
+            library='LibrePCB_Base.lplib',
             diameter=config['diameter'],
             height=config['height'],
             pitch=config['pitch'],
@@ -359,7 +359,7 @@ def _uuid(identifier: str) -> str:
             create_date='2019-12-29T14:14:11Z',
         )
         generate_dev(
-            dirpath='out/capacitors_radial_tht/dev',
+            library='LibrePCB_Base.lplib',
             diameter=config['diameter'],
             height=config['height'],
             pitch=config['pitch'],

diff --git a/generate_chip.py b/generate_chip.py
@@ -171,7 +171,7 @@ def __init__(
 
 
 def generate_pkg(
-    dirpath: str,
+    library: str,
     author: str,
     name: str,
     description: str,
@@ -480,7 +480,7 @@ def add_footprint_variant(
 
         lines.append(')')
 
-        pkg_dir_path = path.join(dirpath, uuid_pkg)
+        pkg_dir_path = path.join('out', library, category, uuid_pkg)
         if not (path.exists(pkg_dir_path) and path.isdir(pkg_dir_path)):
             makedirs(pkg_dir_path)
         with open(path.join(pkg_dir_path, '.librepcb-pkg'), 'w') as f:
@@ -491,7 +491,7 @@ def add_footprint_variant(
 
 
 def generate_dev(
-    dirpath: str,
+    library: str,
     author: str,
     name: str,
     description: str,
@@ -540,7 +540,7 @@ def _uuid(identifier: str) -> str:
             lines.append(' (pad {} (signal {}))'.format(pad, signal))
         lines.append(')')
 
-        dev_dir_path = path.join(dirpath, uuid_dev)
+        dev_dir_path = path.join('out', library, category, uuid_dev)
         if not (path.exists(dev_dir_path) and path.isdir(dev_dir_path)):
             makedirs(dev_dir_path)
         with open(path.join(dev_dir_path, '.librepcb-dev'), 'w') as f:
@@ -551,15 +551,9 @@ def _uuid(identifier: str) -> str:
 
 
 if __name__ == '__main__':
-    def _make(dirpath: str) -> None:
-        if not (path.exists(dirpath) and path.isdir(dirpath)):
-            makedirs(dirpath)
-    _make('out')
-    _make('out/chip')
-    _make('out/chip/pkg')
     # Chip resistors (RESC)
     generate_pkg(
-        dirpath='out/chip/pkg',
+        library='LibrePCB_Base.lplib',
         author='Danilo B.',
         name='RESC{size_metric} ({size_imperial})',
         description='Generic chip resistor {size_metric} (imperial {size_imperial}).\\n\\n'
@@ -585,7 +579,7 @@ def _make(dirpath: str) -> None:
     )
     # J-Lead resistors (RESJ)
     generate_pkg(
-        dirpath='out/chip/pkg',
+        library='LibrePCB_Base.lplib',
         author='Danilo B.',
         name='RESJ{size_metric} ({size_imperial})',
         description='Generic J-lead resistor {size_metric} (imperial {size_imperial}).\\n\\n'
@@ -604,7 +598,7 @@ def _make(dirpath: str) -> None:
     # and KEMET documentation: https://content.kemet.com/datasheets/KEM_T2005_T491.pdf
     # (see Table 2: Land Dimensions / Courtyard)
     generate_pkg(
-        dirpath='out/chip/pkg',
+        library='LibrePCB_Base.lplib',
         author='Danilo B.',
         name='CAPPM{length}X{width}X{height}L{lead_length}X{lead_width}',
         description='Generic polarized molded inward-L capacitor (EIA {meta[eia]}).\\n\\n'
@@ -680,9 +674,8 @@ def _make(dirpath: str) -> None:
         create_date='2019-11-18T21:56:00Z',
     )
     # Generic devices
-    _make('out/chip/dev')
     generate_dev(
-        dirpath='out/chip/dev',
+        library='LibrePCB_Base.lplib',
         author='Danilo B.',
         name='Resistor {size_metric} ({size_imperial})',
         description='Generic SMD resistor {size_metric} (imperial {size_imperial}).',