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ariane to cva6 #87

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ariane to cva6 #87

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0a002e8
switch from ariane to cva6
whutddk Jul 28, 2020
70e13ac
add file list of pmp
whutddk Jul 30, 2020
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14 changes: 7 additions & 7 deletions piton/design/chip/tile/rtl/tile.v.pyv
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Original file line number Diff line number Diff line change
Expand Up @@ -902,7 +902,7 @@ if (TILE_TYPE == `PICORV32_TILE) begin : g_picorv32_core
end
endgenerate
generate
if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core
if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_cva6_core
//////////////////////
// Ariane RV64 Core //
//////////////////////
Expand Down Expand Up @@ -972,7 +972,7 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core
transducer_l15_rqtype == `PCX_REQTYPE_IFILL &&
~transducer_l15_invalidate_cacheline) ? `MSG_DATA_SIZE_32B : `MSG_DATA_SIZE_16B;

wire [63:0] ariane_bootaddr;
wire [63:0] cva6_bootaddr;

<%

Expand Down Expand Up @@ -1002,7 +1002,7 @@ if PITON_ARIANE:
else:
execBase += "64'h" + cacheBase
execLength += "64'h" + cacheLength
if devices[i]["name"] == "ariane_debug":
if devices[i]["name"] == "cva6_debug":
dmBase = "%X" % devices[i]["base"]
dmLength = "%X" % devices[i]["length"]
numRules += 1
Expand All @@ -1012,7 +1012,7 @@ if PITON_ARIANE:
else:
execBase += "64'h" + dmBase
execLength += "64'h" + dmLength
if devices[i]["name"] == "ariane_bootrom":
if devices[i]["name"] == "cva6_bootrom":
romBase = "%X" % devices[i]["base"]
romLength = "%X" % devices[i]["length"]
numRules += 1
Expand All @@ -1031,11 +1031,11 @@ bootAddr = cacheBase
if romIsPresent:
bootAddr = romBase

print(" assign ariane_bootaddr = 64'h%s;" % bootAddr)
print(" assign cva6_bootaddr = 64'h%s;" % bootAddr)
%>


ariane_verilog_wrap #(
cva6_verilog_wrap #(
<%
str = '''
.DmBaseAddress ( 64'h%s ),
Expand All @@ -1052,7 +1052,7 @@ print(str)
.clk_i ( clk_gated ),
.reset_l ( rst_n_f ),
.spc_grst_l ( spc_grst_l ),
.boot_addr_i ( ariane_bootaddr ),
.boot_addr_i ( cva6_bootaddr ),
.hart_id_i ( {{64-`JTAG_FLATID_WIDTH{1'b0}}, flat_tileid} ),
.irq_i ( irq_i ),
.ipi_i ( ipi_i ),
Expand Down
2 changes: 1 addition & 1 deletion piton/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ module noc_axilite_bridge #(
// note that the accesses are still 64bit, but the
// write-enables are generated according to the access size
parameter SLAVE_RESP_BYTEWIDTH = 4,
// swap endianess, needed when used in conjunction with a little endian core like Ariane
// swap endianess, needed when used in conjunction with a little endian core like Cva6
parameter SWAP_ENDIANESS = 0,
// shift unaligned read data
parameter ALIGN_RDATA = 1
Expand Down
92 changes: 46 additions & 46 deletions piton/design/chipset/rtl/chipset_impl.v.pyv
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Expand Up @@ -1128,14 +1128,14 @@ fake_uart fake_uart (
assign irq_sources = {net_interrupt, uart_interrupt};

// this is for selecting the right bootrom (1: baremetal, 0: linux)
wire ariane_boot_sel;
wire cva6_boot_sel;
`ifdef PITON_FPGA_SYNTH
assign ariane_boot_sel = uart_boot_en;
assign cva6_boot_sel = uart_boot_en;
`else
`ifdef ARIANE_SIM_LINUX_BOOT
assign ariane_boot_sel = 1'b0;
assign cva6_boot_sel = 1'b0;
`else
assign ariane_boot_sel = 1'b1;
assign cva6_boot_sel = 1'b1;
`endif
`endif

Expand All @@ -1145,16 +1145,16 @@ RomBase = 0
ClintBase = 0
PlicBase = 0
for i in range(len(devices)):
if devices[i]["name"] == "ariane_debug":
if devices[i]["name"] == "cva6_debug":
DmBase = devices[i]["base"]
if devices[i]["name"] == "ariane_bootrom":
if devices[i]["name"] == "cva6_bootrom":
RomBase = devices[i]["base"]
if devices[i]["name"] == "ariane_clint":
if devices[i]["name"] == "cva6_clint":
ClintBase = devices[i]["base"]
if devices[i]["name"] == "ariane_plic":
if devices[i]["name"] == "cva6_plic":
PlicBase = devices[i]["base"]
str = '''
riscv_peripherals #(
cva6_riscv_peripherals #(
.DataWidth ( `NOC_DATA_WIDTH ),
.NumHarts ( `NUM_TILES ),
.NumSources ( 2 ),
Expand All @@ -1167,32 +1167,32 @@ str = '''
.clk_i ( chipset_clk ),
.rst_ni ( chipset_rst_n ),
.testmode_i ( 1'b0 ),
.buf_ariane_debug_noc2_data_i ( buf_ariane_debug_noc2_data ),
.buf_ariane_debug_noc2_valid_i ( buf_ariane_debug_noc2_valid ),
.ariane_debug_buf_noc2_ready_o ( ariane_debug_buf_noc2_ready ),
.ariane_debug_buf_noc3_data_o ( ariane_debug_buf_noc3_data ),
.ariane_debug_buf_noc3_valid_o ( ariane_debug_buf_noc3_valid ),
.buf_ariane_debug_noc3_ready_i ( buf_ariane_debug_noc3_ready ),
.buf_ariane_bootrom_noc2_data_i ( buf_ariane_bootrom_noc2_data ),
.buf_ariane_bootrom_noc2_valid_i ( buf_ariane_bootrom_noc2_valid ),
.ariane_bootrom_buf_noc2_ready_o ( ariane_bootrom_buf_noc2_ready ),
.ariane_bootrom_buf_noc3_data_o ( ariane_bootrom_buf_noc3_data ),
.ariane_bootrom_buf_noc3_valid_o ( ariane_bootrom_buf_noc3_valid ),
.buf_ariane_bootrom_noc3_ready_i ( buf_ariane_bootrom_noc3_ready ),
.buf_ariane_clint_noc2_data_i ( buf_ariane_clint_noc2_data ),
.buf_ariane_clint_noc2_valid_i ( buf_ariane_clint_noc2_valid ),
.ariane_clint_buf_noc2_ready_o ( ariane_clint_buf_noc2_ready ),
.ariane_clint_buf_noc3_data_o ( ariane_clint_buf_noc3_data ),
.ariane_clint_buf_noc3_valid_o ( ariane_clint_buf_noc3_valid ),
.buf_ariane_clint_noc3_ready_i ( buf_ariane_clint_noc3_ready ),
.buf_ariane_plic_noc2_data_i ( buf_ariane_plic_noc2_data ),
.buf_ariane_plic_noc2_valid_i ( buf_ariane_plic_noc2_valid ),
.ariane_plic_buf_noc2_ready_o ( ariane_plic_buf_noc2_ready ),
.ariane_plic_buf_noc3_data_o ( ariane_plic_buf_noc3_data ),
.ariane_plic_buf_noc3_valid_o ( ariane_plic_buf_noc3_valid ),
.buf_ariane_plic_noc3_ready_i ( buf_ariane_plic_noc3_ready ),
.buf_cva6_debug_noc2_data_i ( buf_cva6_debug_noc2_data ),
.buf_cva6_debug_noc2_valid_i ( buf_cva6_debug_noc2_valid ),
.cva6_debug_buf_noc2_ready_o ( cva6_debug_buf_noc2_ready ),
.cva6_debug_buf_noc3_data_o ( cva6_debug_buf_noc3_data ),
.cva6_debug_buf_noc3_valid_o ( cva6_debug_buf_noc3_valid ),
.buf_cva6_debug_noc3_ready_i ( buf_cva6_debug_noc3_ready ),
.buf_cva6_bootrom_noc2_data_i ( buf_cva6_bootrom_noc2_data ),
.buf_cva6_bootrom_noc2_valid_i ( buf_cva6_bootrom_noc2_valid ),
.cva6_bootrom_buf_noc2_ready_o ( cva6_bootrom_buf_noc2_ready ),
.cva6_bootrom_buf_noc3_data_o ( cva6_bootrom_buf_noc3_data ),
.cva6_bootrom_buf_noc3_valid_o ( cva6_bootrom_buf_noc3_valid ),
.buf_cva6_bootrom_noc3_ready_i ( buf_cva6_bootrom_noc3_ready ),
.buf_cva6_clint_noc2_data_i ( buf_cva6_clint_noc2_data ),
.buf_cva6_clint_noc2_valid_i ( buf_cva6_clint_noc2_valid ),
.cva6_clint_buf_noc2_ready_o ( cva6_clint_buf_noc2_ready ),
.cva6_clint_buf_noc3_data_o ( cva6_clint_buf_noc3_data ),
.cva6_clint_buf_noc3_valid_o ( cva6_clint_buf_noc3_valid ),
.buf_cva6_clint_noc3_ready_i ( buf_cva6__clint_noc3_ready ),
.buf_cva6_plic_noc2_data_i ( buf_cva6_plic_noc2_data ),
.buf_cva6_plic_noc2_valid_i ( buf_cva6_plic_noc2_valid ),
.cva6_plic_buf_noc2_ready_o ( cva6_plic_buf_noc2_ready ),
.cva6_plic_buf_noc3_data_o ( cva6_plic_buf_noc3_data ),
.cva6_plic_buf_noc3_valid_o ( cva6_plic_buf_noc3_valid ),
.buf_cva6_plic_noc3_ready_i ( buf_cva6_plic_noc3_ready ),
// This selects either the BM or linux bootrom
.ariane_boot_sel_i ( ariane_boot_sel ),
.cva6_boot_sel_i ( cva6_boot_sel ),
// Debug sigs to cores
.ndmreset_o ( ndmreset_o ),
.dmactive_o ( dmactive_o ),
Expand Down Expand Up @@ -1221,21 +1221,21 @@ print str
`else

// tie off unused sigs
assign ariane_debug_buf_noc2_ready = 1'b0;
assign ariane_debug_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign ariane_debug_buf_noc3_valid = 1'b0;
assign cva6_debug_buf_noc2_ready = 1'b0;
assign cva6_debug_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign cva6_debug_buf_noc3_valid = 1'b0;

assign ariane_bootrom_buf_noc2_ready = 1'b0;
assign ariane_bootrom_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign ariane_bootrom_buf_noc3_valid = 1'b0;
assign cva6_bootrom_buf_noc2_ready = 1'b0;
assign cva6_bootrom_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign cva6_bootrom_buf_noc3_valid = 1'b0;

assign ariane_clint_buf_noc2_ready = 1'b0;
assign ariane_clint_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign ariane_clint_buf_noc3_valid = 1'b0;
assign cva6_clint_buf_noc2_ready = 1'b0;
assign cva6_clint_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign cva6_clint_buf_noc3_valid = 1'b0;

assign ariane_plic_buf_noc2_ready = 1'b0;
assign ariane_plic_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign ariane_plic_buf_noc3_valid = 1'b0;
assign cva6_plic_buf_noc2_ready = 1'b0;
assign cva6_plic_buf_noc3_data = `NOC_DATA_WIDTH'b0;
assign cva6_plic_buf_noc3_valid = 1'b0;

`endif

Expand Down
14 changes: 7 additions & 7 deletions piton/design/chipset/xilinx/genesys2/devices_ariane.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ specific language governing permissions and limitations under the License.

Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
Date: 26.11.2018
Description: Peripheral address map for OpenPiton+Ariane configurations.
Description: Peripheral address map for OpenPiton+Cva6 configurations.
-->
<devices>
<!--The first entry should always be the filter/chip to xbar connection-->
Expand Down Expand Up @@ -50,35 +50,35 @@ Description: Peripheral address map for OpenPiton+Ariane configurations.
<base>0xfff0d00000</base>
<length>0x100000</length>
</port>
<!-- note: the following modules are ariane-specific and are only instantiated in HW when using the ariane core -->
<!-- note: the following modules are cva6-specific and are only instantiated in HW when using the cva6 core -->
<port>
<!-- this is the shared debug module for JTAG access to all cores -->
<name>ariane_debug</name>
<name>cva6_debug</name>
<base>0xfff1000000</base>
<length>0x1000</length>
<stream_accessible/>
</port>
<port>
<!-- this is the shared bootrom (contains DTB that is generated for the current platform config) -->
<name>ariane_bootrom</name>
<name>cva6_bootrom</name>
<base>0xfff1010000</base>
<length>0x10000</length>
<stream_accessible/>
</port>
<port>
<!-- core local interrupt controller with real-time counter. this is shared among all cores -->
<name>ariane_clint</name>
<name>cva6_clint</name>
<base>0xfff1020000</base>
<length>0xc0000</length>
<stream_accessible/>
</port>
<!-- platform level interrupt controller -->
<port>
<name>ariane_plic</name>
<name>cva6_plic</name>
<base>0xfff1100000</base>
<length>0x4000000</length>
<stream_accessible/>
</port>
<!-- end ariane specific periphs -->
<!-- end cva6 specific periphs -->
</devices>

14 changes: 7 additions & 7 deletions piton/design/chipset/xilinx/vcu118/devices_ariane.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ specific language governing permissions and limitations under the License.

Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
Date: 26.11.2018
Description: Peripheral address map for OpenPiton+Ariane configurations.
Description: Peripheral address map for OpenPiton+Cva6 configurations.
-->
<devices>
<!--The first entry should always be the filter/chip to xbar connection-->
Expand Down Expand Up @@ -49,31 +49,31 @@ Description: Peripheral address map for OpenPiton+Ariane configurations.
<base>0xfff0d00000</base>
<length>0x100000</length>
</port> -->
<!-- note: the following modules are ariane-specific and are only instantiated in HW when using the ariane core -->
<!-- note: the following modules are cva6-specific and are only instantiated in HW when using the cva6 core -->
<port>
<!-- this is the shared debug module for JTAG access to all cores -->
<name>ariane_debug</name>
<name>cva6_debug</name>
<base>0xfff1000000</base>
<length>0x1000</length>
</port>
<port>
<!-- this is the shared bootrom (contains DTB that is generated for the current platform config) -->
<name>ariane_bootrom</name>
<name>cva6_bootrom</name>
<base>0xfff1010000</base>
<length>0x10000</length>
</port>
<port>
<!-- core local interrupt controller with real-time counter. this is shared among all cores -->
<name>ariane_clint</name>
<name>cva6_clint</name>
<base>0xfff1020000</base>
<length>0xc0000</length>
</port>
<!-- platform level interrupt controller -->
<port>
<name>ariane_plic</name>
<name>cva6_plic</name>
<base>0xfff1030000</base>
<length>0x4000000</length>
</port>
<!-- end ariane specific periphs -->
<!-- end cva6 specific periphs -->
</devices>

2 changes: 1 addition & 1 deletion piton/design/common/rtl/synchronizer.v
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Expand Up @@ -53,7 +53,7 @@ input wire [SIZE-1:0] presyncdata;
output reg [SIZE-1:0] syncdata;

`ifdef PITON_ARIANE
// this prevents SV assertion failures in Ariane
// this prevents SV assertion failures in Cva6
// pragma translate_off
`define SIM_RST_INIT
// pragma translate_on
Expand Down
2 changes: 1 addition & 1 deletion piton/design/include/l15.h.pyv
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Expand Up @@ -56,7 +56,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from pyhplib import *

if 'PITON_ARIANE' in globals():
print("// this is used in the ariane SV packages to derive the parameterization")
print("// this is used in the Cva6 SV packages to derive the parameterization")
print("`define CONFIG_L1D_CACHELINE_WIDTH %d" % 128) # constant at the moment
print("`define CONFIG_L1I_CACHELINE_WIDTH %d" % 256) # constant at the moment
print("`define CONFIG_L15_SIZE %d" % CONFIG_L15_SIZE)
Expand Down
14 changes: 7 additions & 7 deletions piton/design/xilinx/f1/devices_ariane.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ specific language governing permissions and limitations under the License.

Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
Date: 26.11.2018
Description: Peripheral address map for OpenPiton+Ariane configurations.
Description: Peripheral address map for OpenPiton+Cva6 configurations.
-->
<devices>
<!--The first entry should always be the filter/chip to xbar connection-->
Expand Down Expand Up @@ -51,35 +51,35 @@ Description: Peripheral address map for OpenPiton+Ariane configurations.
<base>0xfff0d00000</base>
<length>0x100000</length>
</port> -->
<!-- note: the following modules are ariane-specific and are only instantiated in HW when using the ariane core -->
<!-- note: the following modules are cva6-specific and are only instantiated in HW when using the cva6 core -->
<port>
<!-- this is the shared debug module for JTAG access to all cores -->
<name>ariane_debug</name>
<name>cva6_debug</name>
<base>0xfff1000000</base>
<length>0x1000</length>
<stream_accessible/>
</port>
<port>
<!-- this is the shared bootrom (contains DTB that is generated for the current platform config) -->
<name>ariane_bootrom</name>
<name>cva6_bootrom</name>
<base>0xfff1010000</base>
<length>0x10000</length>
<stream_accessible/>
</port>
<port>
<!-- core local interrupt controller with real-time counter. this is shared among all cores -->
<name>ariane_clint</name>
<name>cva6_clint</name>
<base>0xfff1020000</base>
<length>0xc0000</length>
<stream_accessible/>
</port>
<!-- platform level interrupt controller -->
<port>
<name>ariane_plic</name>
<name>cva6_plic</name>
<base>0xfff1100000</base>
<length>0x4000000</length>
<stream_accessible/>
</port>
<!-- end ariane specific periphs -->
<!-- end cva6 specific periphs -->
</devices>

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