Dual-issue-pipelined-multimedia-CELL-processor-Architecture

Created a pipelined version of CELL SPU microprocessor using System Verilog. Specifications: 128 bit processor 73 instructions (Included multimedia and general processing instructions- GPU and CPU) 12 stage pipelining Dual issue instruction architecture SIMD processing Local Store (Memory) - 32 KB L1 cache- Direct Mapped- 4 KB Branch Prediction - Dynamic Branch Prediction (BTB)