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4 Bit ALU Implementation in Verilog

As part of a mini project, I made an ALU which can take combinations of 4 bits, and generate/ perform any of the mentioned 16 operations. This happens because of the conditional statement which checks the combination of the 4 bits. To run the code, simply download all the files, put them in a folder and import the folder in Vivado.

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Implementation of an ALU with 4 bits in Verilog using Vivado.

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