flow: simplify, DONT_USE_LIBS->LIB_FILES_EXTRACTED, DONT_USE_SC_LIB->…

…SC_LIB_FILE

Signed-off-by: Emil J. Tywoniak <emil@tywoniak.eu>

docs/user/FlowVariables.md

@@ -86,7 +86,7 @@ configuration file.
 | <a name="DFF_LIB_FILES"></a>DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | |
 | <a name="DIE_AREA"></a>DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | |
 | <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | |
-| <a name="DONT_USE_LIBS"></a>DONT_USE_LIBS| Set liberty files as `dont_use`.| | |
+| <a name="LIB_FILES_EXTRACTED"></a>LIB_FILES| All technology mapping liberty files to use, extracted into object directory. Set by Makefile.| | |
 | <a name="DPO_MAX_DISPLACEMENT"></a>DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| |
 | <a name="ENABLE_DPO"></a>ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| |
 | <a name="EQUIVALENCE_CHECK"></a>EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| |
@@ -334,7 +334,7 @@ configuration file.
 - [DESIGN_NICKNAME](#DESIGN_NICKNAME)
 - [DFF_LIB_FILES](#DFF_LIB_FILES)
 - [DONT_USE_CELLS](#DONT_USE_CELLS)
-- [DONT_USE_LIBS](#DONT_USE_LIBS)
+- [LIB_FILES_EXTRACTED](#LIB_FILES_EXTRACTED)
 - [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT)
 - [ENABLE_DPO](#ENABLE_DPO)
 - [FASTROUTE_TCL](#FASTROUTE_TCL)

flow/Makefile

@@ -286,9 +286,8 @@ WRAPPED_LEFS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/lef/$(lef:.le
 WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_mod.lib))
 export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS)
 export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS)
-
-export DONT_USE_LIBS   = $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES))))
-export DONT_USE_SC_LIB ?= $(firstword $(DONT_USE_LIBS))
+export LIB_FILES_EXTRACTED := $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES))))
+export SC_LIB_FILE ?= $(firstword $(LIB_FILES_EXTRACTED))
 
 # Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS
 STREAM_SYSTEM ?= GDS
@@ -355,12 +354,16 @@ versions.txt:
 # Create temporary Liberty files which have the proper dont_use properties set
 # For use with Yosys and ABC
 .SECONDEXPANSION:
-$(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
+$(LIB_FILES_EXTRACTED): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
 	@mkdir -p $(OBJECTS_DIR)/lib
-	$(UTILS_DIR)/preprocessLib.py -i $^ -o $@
+	@if echo "$<" | grep -q "\.gz$$"; then \
+		gunzip -c $< > $@; \
+	else \
+		cp $< $@; \
+	fi
 
 $(OBJECTS_DIR)/lib/merged.lib:
-	$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
+	$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(LIB_FILES_EXTRACTED) > $@
 
 # Pre-process KLayout tech
 # ==============================================================================
@@ -467,7 +470,7 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
 	mkdir -p $(dir $@)
 	echo $(ABC_CLOCK_PERIOD_IN_PS) > $@
 
-YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
+YOSYS_DEPENDENCIES=$(LIB_FILES_EXTRACTED) $(WRAPPED_LIBS) $(SC_LIB_FILE) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
 
 .PHONY: yosys-dependencies
 yosys-dependencies: $(YOSYS_DEPENDENCIES)

flow/platforms/asap7/config.mk

@@ -264,7 +264,7 @@ export LIB_FILES             += $(ADDITIONAL_LIBS)
 export DB_FILES              += $(realpath $($(CORNER)_DB_FILES))
 export TEMPERATURE            = $($(CORNER)_TEMPERATURE)
 export VOLTAGE                = $($(CORNER)_VOLTAGE)
-export DONT_USE_SC_LIB        = $(OBJECTS_DIR)/lib/merged.lib
+export SC_LIB_FILE            = $(OBJECTS_DIR)/lib/merged.lib
 
 # ---------------------------------------------------------
 #  IR Drop

flow/scripts/floorplan.tcl

@@ -126,7 +126,7 @@ if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
 
   write_verilog $::env(RESULTS_DIR)/2_pre_abc_timing.v
 
-  restructure -target timing -liberty_file $::env(DONT_USE_SC_LIB) \
+  restructure -target timing -liberty_file $::env(SC_LIB_FILE) \
               -work_dir $::env(RESULTS_DIR)
 
   write_verilog $::env(RESULTS_DIR)/2_post_abc_timing.v
@@ -171,7 +171,7 @@ if { [env_var_equals RESYNTH_AREA_RECOVER 1] } {
   set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
   set tiehi_port $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1]
 
-  restructure -liberty_file $::env(DONT_USE_SC_LIB) -target "area" \
+  restructure -liberty_file $::env(SC_LIB_FILE) -target "area" \
         -tiehi_port $tiehi_port \
         -tielo_port $tielo_port \
         -work_dir $::env(RESULTS_DIR)

flow/scripts/synth.tcl

@@ -67,7 +67,7 @@ foreach cell $::env(DONT_USE_CELLS) {
 if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {
   dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
 } else {
-  dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
+  dfflibmap -liberty $::env(SC_LIB_FILE) {*}$dfflibmap_args
 }
 opt
 

flow/scripts/synth_preamble.tcl

@@ -38,7 +38,7 @@ foreach file $::env(VERILOG_FILES) {
 
 # Read standard cells and macros as blackbox inputs
 # These libs have their dont_use properties set accordingly
-read_liberty -lib {*}$::env(DONT_USE_LIBS)
+read_liberty -lib {*}$::env(LIB_FILES_EXTRACTED)
 
 # Apply toplevel parameters (if exist)
 if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} {
@@ -74,7 +74,7 @@ if {$::env(ABC_AREA)} {
 # Technology mapping for cells
 # ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't
 set abc_args [list -script $abc_script \
-      -liberty $::env(DONT_USE_SC_LIB) \
+      -liberty $::env(SC_LIB_FILE) \
       -constr $::env(OBJECTS_DIR)/abc.constr]
 
 # Exclude dont_use cells. This includes macros that are specified via
@@ -98,7 +98,7 @@ if {[env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] && [file isfile $::env(
 
 # Create argument list for stat
 set stat_libs ""
-foreach lib $::env(DONT_USE_LIBS) {
+foreach lib $::env(LIB_FILES_EXTRACTED) {
   append stat_libs "-liberty $lib "
 }
 

flow/scripts/synth_stats.tcl

@@ -23,7 +23,7 @@ proc write_keep_hierarchy {} {
   if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {
     dfflibmap -liberty $::env(DFF_LIB_FILE)
   } else {
-    dfflibmap -liberty $::env(DONT_USE_SC_LIB)
+    dfflibmap -liberty $::env(SC_LIB_FILE)
   }
   puts "abc [join $abc_args " "]"
   abc {*}$abc_args

flow/scripts/variables.yaml

@@ -125,7 +125,7 @@ LIB_FILES:
     input and output characteristics, timing and power definitions for each cell.
 DONT_USE_CELLS:
   description: >
-    Dont use cells eases pin access in detailed routing.
+    List of cells to mark dont_use to e.g. ease pin access in detailed routing.
 SYNTH_GUT:
   description: >
     Load design and remove all internal logic before doing synthesis. This
@@ -547,9 +547,9 @@ CDL_FILES:
 DFF_LIB_FILES:
   description: >
     Technology mapping liberty files for flip-flops.
-DONT_USE_LIBS:
+LIB_FILES_EXTRACTED:
   description: >
-    Set liberty files as `dont_use`.
+    All technology mapping liberty files to use, extracted into object directory. Set by Makefile.
 PRESERVE_CELLS:
   description: >
     Mark modules to keep from getting removed in flattening.