2D-Parametric-Systolic-Array

Digital design and verification of parametric n × n systolic array for matrix multiplication in SystemVerilog using Xilinx Vivado and Mentor QuestaSim. In addition to the RTL, the repository includes two self-checking testbenches (N = 4 and N = 8) that generate random matrices and inject them into the array. Additionally, a do file is provided for execution using QuestaSim.