Interface and configuration

Both the SAURIA accelerator and the uDMA engine have an AXI4-Lite bus for configuration. The following link shows the SAURIA configuration signals and their mapping for an 8x16 (8 rows; 16 cols) array.

It's important to consider that this exact mapping depends on the hardware parameters, so it is only valid for the 8x16 case. For different arrangements of the accelerator, the signal descriptions and region offsets will be the same, but the number of bits used for each signal will vary, so the mapping will change. Just as in the example, the signals are mapped in contiguous locations, so it is relatively easy to extrapolate this mapping to any arbitrary SAURIA configuration.