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move llvm ir in debug.rs
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ctiedt committed Sep 14, 2023
1 parent 56b5df0 commit 98d249e
Showing 1 changed file with 19 additions and 18 deletions.
37 changes: 19 additions & 18 deletions compiler/cli/src/debug.rs
Original file line number Diff line number Diff line change
Expand Up @@ -60,15 +60,16 @@ pub(crate) enum Options {
/// Low-Level Intermediate Representation
Lir(PathAndTracing),

/// LLVM Intermediate Representation
#[cfg(feature = "inkwell")]
LlvmIr(OnlyPath),


/// Optimized Low-Level Intermediate Representation
OptimizedLir(PathAndTracing),

/// VM Byte Code
VmByteCode(PathAndTracing),

/// LLVM Intermediate Representation
#[cfg(feature = "inkwell")]
LlvmIr(OnlyPath),

#[command(subcommand)]
Gold(Gold),
Expand Down Expand Up @@ -150,25 +151,25 @@ pub(crate) fn debug(options: Options) -> ProgramResult {
lir.ok()
.map(|(lir, _)| RichIr::for_lir(&module, &lir, &tracing))
}
#[cfg(feature = "inkwell")]
Options::LlvmIr(options) => {
let module = module_for_path(options.path.clone())?;
let llvm_ir = db.llvm_ir(module.clone());
llvm_ir.ok()
}
Options::OptimizedLir(options) => {
let module = module_for_path(options.path.clone())?;
let tracing = options.to_tracing_config();
let lir = db.optimized_lir(module.clone(), tracing.clone());
lir.ok()
.map(|(lir, _)| RichIr::for_lir(&module, &lir, &tracing))
.map(|(lir, _)| RichIr::for_lir(&module, &lir, &tracing))
}
Options::VmByteCode(options) => {
let module = module_for_path(options.path.clone())?;
let tracing = options.to_tracing_config();
let (vm_byte_code, _) = compile_byte_code(&db, module.clone(), tracing.clone());
Some(RichIr::for_byte_code(&module, &vm_byte_code, &tracing))
}
#[cfg(feature = "inkwell")]
Options::LlvmIr(options) => {
let module = module_for_path(options.path.clone())?;
let llvm_ir = db.llvm_ir(module.clone());
llvm_ir.ok()
}
Options::Gold(options) => return options.run(&db),
};

Expand Down Expand Up @@ -356,12 +357,6 @@ impl GoldOptions {
let lir = RichIr::for_lir(&module, &lir, &Self::TRACING_CONFIG);
visit("LIR", lir.text);

#[cfg(feature = "inkwell")]
{
let llvm_ir = db.llvm_ir(module.clone()).unwrap();
visit("LLVM IR", llvm_ir.text);
}

let (optimized_lir, _) = db
.optimized_lir(module.clone(), Self::TRACING_CONFIG.clone())
.unwrap();
Expand All @@ -376,6 +371,12 @@ impl GoldOptions {
"VM Byte Code",
Self::format_byte_code(&vm_byte_code, &vm_byte_code_rich_ir),
);

#[cfg(feature = "inkwell")]
{
let llvm_ir = db.llvm_ir(module.clone()).unwrap();
visit("LLVM IR", llvm_ir.text);
}
}
Ok(())
}
Expand Down

1 comment on commit 98d249e

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@jwbot jwbot commented on 98d249e Sep 14, 2023

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Compiler

Benchmark suite Current: 98d249e Previous: 536cdae Ratio
Time: Compiler/hello_world 24767697 ns/iter (± 724261) 23599594 ns/iter (± 651239) 1.05
Time: Compiler/fibonacci 203287275 ns/iter (± 13572086) 175345948 ns/iter (± 1681495) 1.16
Time: VM Runtime/hello_world 60851 ns/iter (± 31417) 56001 ns/iter (± 5412) 1.09
Time: VM Runtime/fibonacci/15 349236936 ns/iter (± 14170389) 289040793 ns/iter (± 649538) 1.21
Time: VM Runtime/PLB/binarytrees/6 1626778089 ns/iter (± 111575180) 1340589146 ns/iter (± 3594009) 1.21

This comment was automatically generated by workflow using github-action-benchmark.

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