Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.
This repository contains four parts:
- The Lion library: a pipelined RISC-V core.
- lion-formal: formally verify the core using riscv-formal.
- lion-soc: a System-on-Chip demonstrating usage of the Lion core on the VELDT.
- lion-metric: Observe Yosys synthesis metrics on the Lion Core.
- Add
lion
to build depends section of Cabal file - import module in source files
import Lion.Core
When connecting the core
to memory and peripherals, ensure single cycle latency.
git clone https://github.com/standardsemiconductor/lion.git
cd lion
git submodule update --init
- Architecture: RV32I (no FENCE, ECALL, EBREAK)
- Configurable ALU adder and subtractor: use a generic (+) and (-) or SB_MAC16 hard IP
All features will be added in a configurable manner extending the base RV32I configuration noted above
- Zicsr, Control and Status Register (CSR) Instructions
- CSR registers
- RV32IM
Check out the Lion Development project to see which features are in progress.