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Integrate everything in Sgmii.sgmii
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jvnknvlgl committed Jun 12, 2024
1 parent aa75800 commit 4a4504b
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Showing 3 changed files with 39 additions and 20 deletions.
38 changes: 21 additions & 17 deletions clash-cores/src/Clash/Cores/Sgmii/AutoNeg.hs
Original file line number Diff line number Diff line change
Expand Up @@ -42,17 +42,20 @@ data AutoNegState dom
, _rxConfRegs :: Vec 3 ConfReg
, _failTimer :: Timeout dom
, _linkTimer :: Timeout dom
, _txConfReg :: ConfReg
}
| IdleDetect
{ _rudis :: Vec 3 Rudi
, _rxConfRegs :: Vec 3 ConfReg
, _failTimer :: Timeout dom
, _linkTimer :: Timeout dom
, _txConfReg :: ConfReg
}
| LinkOk
{ _rudis :: Vec 3 Rudi
, _rxConfRegs :: Vec 3 ConfReg
, _failTimer :: Timeout dom
, _txConfReg :: ConfReg
}
deriving (Generic, NFDataX, Eq, Show)

Expand Down Expand Up @@ -119,7 +122,7 @@ autoNegT ::
-- | Inputs of the state transition function
(ConfReg, SyncStatus, Maybe Rudi, Maybe ConfReg) ->
-- | Tuple with the new state and the outputs of the state transition function
(AutoNegState dom, (AutoNegState dom, Xmit, Maybe ConfReg))
(AutoNegState dom, (AutoNegState dom, Xmit, ConfReg))
autoNegT self@AnEnable{..} (_, syncStatus, rudi, rxConfRegNew) =
(nextState, out)
where
Expand All @@ -135,7 +138,7 @@ autoNegT self@AnEnable{..} (_, syncStatus, rudi, rxConfRegNew) =
failTimer = if syncStatus == Fail then _failTimer + 1 else 0
xmit = Conf

out = (self, xmit, Just txConfReg)
out = (self, xmit, txConfReg)
autoNegT self@AnRestart{..} (_, syncStatus, rudi, rxConfRegNew) =
(nextState, out)
where
Expand All @@ -153,7 +156,7 @@ autoNegT self@AnRestart{..} (_, syncStatus, rudi, rxConfRegNew) =
failTimer = if syncStatus == Fail then _failTimer + 1 else 0
xmit = Conf

out = (self, xmit, Just 0)
out = (self, xmit, 0)
autoNegT self@AbilityDetect{..} (mrAdvAbility, syncStatus, rudi, rxConfRegNew) =
(nextState, out)
where
Expand All @@ -171,7 +174,7 @@ autoNegT self@AbilityDetect{..} (mrAdvAbility, syncStatus, rudi, rxConfRegNew) =
failTimer = if syncStatus == Fail then _failTimer + 1 else 0
xmit = Conf

out = (self, xmit, Nothing)
out = (self, xmit, txConfReg)
autoNegT self@AcknowledgeDetect{..} (_, syncStatus, rudi, rxConfRegNew) =
(nextState, out)
where
Expand All @@ -184,7 +187,7 @@ autoNegT self@AcknowledgeDetect{..} (_, syncStatus, rudi, rxConfRegNew) =
| abilityMatch rudis rxConfRegs && last rxConfRegs == 0 =
AnEnable rudis rxConfRegs failTimer
| acknowledgeMatch rxConfRegs && consistencyMatch rudis rxConfRegs =
CompleteAcknowledge rudis rxConfRegs failTimer 0
CompleteAcknowledge rudis rxConfRegs failTimer 0 txConfReg
| otherwise = AcknowledgeDetect rudis rxConfRegs failTimer txConfReg

rudis = maybe _rudis (_rudis <<+) rudi
Expand All @@ -193,7 +196,7 @@ autoNegT self@AcknowledgeDetect{..} (_, syncStatus, rudi, rxConfRegNew) =
failTimer = if syncStatus == Fail then _failTimer + 1 else 0
xmit = Conf

out = (self, xmit, Just txConfReg)
out = (self, xmit, txConfReg)
autoNegT self@CompleteAcknowledge{..} (_, syncStatus, rudi, rxConfRegNew) =
(nextState, out)
where
Expand All @@ -204,18 +207,19 @@ autoNegT self@CompleteAcknowledge{..} (_, syncStatus, rudi, rxConfRegNew) =
| abilityMatch rudis rxConfRegs && last rxConfRegs == 0 =
AnEnable rudis rxConfRegs failTimer
| linkTimer == timeout (Proxy @dom) && not (abilityMatch rudis rxConfRegs) =
IdleDetect rudis rxConfRegs failTimer 0
IdleDetect rudis rxConfRegs failTimer 0 _txConfReg
| linkTimer == timeout (Proxy @dom) && last rxConfRegs /= 0 =
IdleDetect rudis rxConfRegs failTimer 0
| otherwise = CompleteAcknowledge rudis rxConfRegs failTimer linkTimer
IdleDetect rudis rxConfRegs failTimer 0 _txConfReg
| otherwise =
CompleteAcknowledge rudis rxConfRegs failTimer linkTimer _txConfReg

rudis = maybe _rudis (_rudis <<+) rudi
rxConfRegs = maybe _rxConfRegs (_rxConfRegs <<+) rxConfRegNew
linkTimer = _linkTimer + 1
failTimer = if syncStatus == Fail then _failTimer + 1 else 0
xmit = Conf

out = (self, xmit, Nothing)
out = (self, xmit, _txConfReg)
autoNegT self@IdleDetect{..} (_, syncStatus, rudi, rxConfRegNew) =
(nextState, out)
where
Expand All @@ -226,31 +230,31 @@ autoNegT self@IdleDetect{..} (_, syncStatus, rudi, rxConfRegNew) =
| abilityMatch rudis rxConfRegs && last rxConfRegs == 0 =
AnEnable rudis rxConfRegs failTimer
| linkTimer == timeout (Proxy @dom) && idleMatch rudis =
LinkOk rudis rxConfRegs failTimer
| otherwise = IdleDetect rudis rxConfRegs failTimer linkTimer
LinkOk rudis rxConfRegs failTimer _txConfReg
| otherwise = IdleDetect rudis rxConfRegs failTimer linkTimer _txConfReg

rudis = maybe _rudis (_rudis <<+) rudi
rxConfRegs = maybe _rxConfRegs (_rxConfRegs <<+) rxConfRegNew
linkTimer = _linkTimer + 1
failTimer = if syncStatus == Fail then _failTimer + 1 else 0
xmit = Idle

out = (self, xmit, Nothing)
out = (self, xmit, _txConfReg)
autoNegT self@LinkOk{..} (_, syncStatus, rudi, rxConfRegNew) = (nextState, out)
where
nextState
| failTimer == timeout (Proxy @dom) =
AnEnable rudis rxConfRegs (timeout (Proxy @dom) - 1)
| rudi == Just Invalid = AnEnable rudis rxConfRegs failTimer
| abilityMatch rudis rxConfRegs = AnEnable rudis rxConfRegs failTimer
| otherwise = LinkOk rudis rxConfRegs failTimer
| otherwise = LinkOk rudis rxConfRegs failTimer _txConfReg

rudis = maybe _rudis (_rudis <<+) rudi
rxConfRegs = maybe _rxConfRegs (_rxConfRegs <<+) rxConfRegNew
failTimer = if syncStatus == Fail then _failTimer + 1 else 0
xmit = Data

out = (self, xmit, Nothing)
out = (self, xmit, _txConfReg)

-- | Function that implements the auto negotiation block as defined in IEEE
-- 802.3 Clause 37
Expand All @@ -265,8 +269,8 @@ autoNeg ::
Signal dom (Maybe Rudi) ->
-- | A new value of 'ConfReg' from 'Sgmii.pcsReceive'
Signal dom (Maybe ConfReg) ->
-- | Tuple containing the new value for 'Xmit' and a possible new 'ConfReg'
Signal dom (Xmit, Maybe ConfReg)
-- | Tuple containing the new value for 'Xmit' and a new 'ConfReg'
Signal dom (Xmit, ConfReg)
autoNeg confReg syncStatus rudi rxConfReg = bundle (xmit, txConfReg)
where
(_, xmit, txConfReg) =
Expand Down
8 changes: 8 additions & 0 deletions clash-cores/src/Clash/Cores/Sgmii/PcsTransmit.hs
Original file line number Diff line number Diff line change
Expand Up @@ -5,13 +5,21 @@ import Clash.Cores.Sgmii.PcsTransmit.CodeGroup
import Clash.Cores.Sgmii.PcsTransmit.OrderedSet
import Clash.Prelude

-- | Takes the signals that are defined in IEEE 802.3 Clause 36 and runs them
-- through the state machines as defined for the PCS transmit block
pcsTransmit ::
(HiddenClockResetEnable dom) =>
-- | The @TX_EN@ signal
Signal dom Bool ->
-- | The @TX_ER@ signal
Signal dom Bool ->
-- | The new data word that needs to be transmitted
Signal dom (BitVector 8) ->
-- | The 'Xmit' signal from 'Sgmii.autoNeg'
Signal dom Xmit ->
-- | The 'ConfReg' from 'Sgmii.autoNeg'
Signal dom ConfReg ->
-- | The 8b/10b encoded output value
Signal dom (BitVector 10)
pcsTransmit txEn txEr dw xmit txConfReg = cg
where
Expand Down
13 changes: 10 additions & 3 deletions clash-cores/src/Clash/Cores/Sgmii/Sgmii.hs
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@ import Clash.Cores.Sgmii.AutoNeg
import Clash.Cores.Sgmii.BitSlip
import Clash.Cores.Sgmii.Common
import Clash.Cores.Sgmii.PcsReceive
import Clash.Cores.Sgmii.PcsTransmit
import Clash.Cores.Sgmii.Sync
import Clash.Prelude

Expand All @@ -13,15 +14,21 @@ import Clash.Prelude
sgmii ::
(HiddenClockResetEnable dom) =>
Signal dom (Index 10) ->
Signal dom Bool ->
Signal dom Bool ->
Signal dom (BitVector 8) ->
Signal dom (BitVector 10) ->
Signal dom (Bool, Bool, BitVector 8)
sgmii bs cg1 =
Signal dom (Bool, Bool, BitVector 8, BitVector 10)
sgmii bs txEn txEr dw cg1 =
bundle
( regMaybe False rxDv
, regMaybe False rxEr
, regMaybe 0 ((fmap . fmap) fromDw dw2)
, cg3
)
where
cg3 = pcsTransmit txEn txEr dw xmit txConfReg

cg2 = bitSlip bs cg1

(rd, dw1, rxEven, syncStatus) =
Expand All @@ -30,5 +37,5 @@ sgmii bs cg1 =
(rxDv, rxEr, dw2, rudi, rxConfReg) =
unbundle $ pcsReceive rd dw1 rxEven syncStatus xmit

(xmit, _) =
(xmit, txConfReg) =
unbundle $ autoNeg (pure 1) syncStatus rudi rxConfReg

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