Remove Synthesize annotations from i2c core

To allow for polymorphism in the domain. Also added `i2cTop` which is a monomorphic i2c core with `makeTopEntity`
clash-lang · Oct 18, 2023 · f08ba82 · f08ba82
1 parent 38fc2ee
commit f08ba82
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diff --git a/clash-cores/src/Clash/Cores/I2C.hs b/clash-cores/src/Clash/Cores/I2C.hs
@@ -6,38 +6,8 @@ import Clash.Prelude hiding (read)
 
 import Clash.Cores.I2C.BitMaster
 import Clash.Cores.I2C.ByteMaster
+import Clash.Annotations.TH
 
-{-# ANN i2c
-  (Synthesize
-    { t_name     = "i2c"
-    , t_inputs   = [ PortName "clk"
-                   , PortName "arst"
-                   , PortName "rst"
-                   , PortName "ena"
-                   , PortName "clkCnt"
-                   , PortName "start"
-                   , PortName "stop"
-                   , PortName "read"
-                   , PortName "write"
-                   , PortName "ackIn"
-                   , PortName "din"
-                     , PortProduct "i2c"
-                        [ PortName "sda"
-                        , PortName "sdaEn"]
-                        ]
-    , t_output   = PortProduct ""
-                     [ PortName "dout"
-                     , PortName "hostAck"
-                     , PortName "busy"
-                     , PortName "al"
-                     , PortName "ackOut"
-                     , PortProduct "i2cO"
-                        [ PortName "scl"
-                        , PortName "sclOEn"
-                        , PortName "sda"
-                        , PortName "sdaOEn"
-                     ]]
-    }) #-}
 -- | Core for I2C communication
 i2c ::
   forall dom .
@@ -91,3 +61,6 @@ i2c clk arst rst ena clkCnt start stop read write ackIn din i2cI = (dout,hostAck
     (_cmdAck,al,_dbout)           = unbundle bitResp
 -- See: https://github.com/clash-lang/clash-compiler/pull/2511
 {-# CLASH_OPAQUE i2c #-}
+
+i2cTop = i2c @System
+makeTopEntity 'i2cTop
diff --git a/clash-cores/src/Clash/Cores/I2C/BitMaster.hs b/clash-cores/src/Clash/Cores/I2C/BitMaster.hs
@@ -52,34 +52,7 @@ type BitMasterI = (Bool,Bool,Unsigned 16,BitCtrlSig,I2CIn)
 -- 3. Contains the SCL and SDA output signals
 type BitMasterO = (BitRespSig,Bool,I2COut)
 
-{-# ANN bitMaster
-  (Synthesize
-    { t_name     = "bitmaster"
-    , t_inputs   = [ PortName "clk"
-                   , PortName "arst"
-                   , PortName "gen"
-                   , PortProduct ""
-                      [ PortName "rst"
-                      , PortName "ena"
-                      , PortName "clkCnt"
-                      , PortProduct ""
-                          [ PortName "cmd"
-                          , PortName "din" ]
-                      , PortName "i2cI" ]
-                   ]
-    , t_output   = PortProduct ""
-                     [ PortProduct ""
-                        [ PortName "cmdAck"
-                        , PortName "al"
-                        , PortName "dout" ]
-                     , PortName "busy"
-                     , PortProduct "i2c"
-                        [ PortName "sda"
-                        , PortName "sdaEn"
-                        , PortName "scl"
-                        , PortName "sclEn" ]
-                     ]
-    }) #-}
+
 bitMaster
   :: KnownDomain dom
   => Clock dom

diff --git a/clash-cores/src/Clash/Cores/I2C/ByteMaster.hs b/clash-cores/src/Clash/Cores/I2C/ByteMaster.hs
@@ -48,29 +48,6 @@ type ByteMasterI = (Bool,Bool,Bool,Bool,Bool,Bool,BitVector 8,BitRespSig)
 -- 4  Bitmaster control signals
 type ByteMasterO = (Bool,Bool,BitVector 8,BitCtrlSig)
 
-{-# ANN byteMaster
-  (Synthesize
-    { t_name     = "bytemaster"
-    , t_inputs   = [ PortName "clk"
-                   , PortName "arst"
-                   , PortName "gen"
-                   , PortProduct ""
-                      [ PortName "rst"
-                      , PortName "start"
-                      , PortName "stop"
-                      , PortName "read"
-                      , PortName "write"
-                      , PortName "ackIn"
-                      , PortName "din"
-                      , PortName "bitResp" ]
-                   ]
-    , t_output   = PortProduct ""
-                     [ PortName "hostAck"
-                     , PortName "ackOut"
-                     , PortName "dout"
-                     , PortName "bitCtrl"
-                     ]
-    }) #-}
 -- | Byte level controller, takes care of correctly executing i2c communication
 -- based on the supplied control signals. It should be instantiated alongside 'bitMaster'.
 -- The outgoing bitCtrl' controls the 'bitMaster' whose 'bitResp' should be supplied

diff --git a/clash-cores/test/Test/Cores/I2C.hs b/clash-cores/test/Test/Cores/I2C.hs
@@ -31,7 +31,7 @@ system0 clk arst = bundle (registerFile,done,fault)
 -- See: https://github.com/clash-lang/clash-compiler/pull/2511
 {-# CLASH_OPAQUE system0 #-}
 
-{-# ANN system Synthesize { t_name = "system", t_inputs = [], t_output = PortName "" } #-}
+{-# ANN system (defSyn "system") #-}
 system :: Signal System (Vec 16 (Unsigned 8), Bool, Bool)
 system = system0 systemClockGen resetGen