Merge pull request #36 from clash-lang/lucas/add-Jtag-Idle

Add `IdleCircuit` instance for `Jtag` Protocol
clash-lang · Sep 18, 2024 · 0ac4a4f · 0ac4a4f
2 parents 390818c + 31e1b75
commit 0ac4a4f
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diff --git a/cabal.project b/cabal.project
@@ -52,7 +52,14 @@ source-repository-package
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-protocols.git
-  tag: eb76cd1be746ae91beff60c0f16d8c1dd888662c
+  tag: 0832a422e77422739401896f6612620d17baa289
+  subdir: clash-protocols
+
+source-repository-package
+  type: git
+  location: https://github.com/clash-lang/clash-protocols.git
+  tag: 0832a422e77422739401896f6612620d17baa289
+  subdir: clash-protocols-base
 
 source-repository-package
   type: git

diff --git a/clash-vexriscv/src/VexRiscv.hs b/clash-vexriscv/src/VexRiscv.hs
@@ -27,6 +27,7 @@ import GHC.IO (unsafePerformIO, unsafeInterleaveIO)
 import GHC.Stack (HasCallStack)
 import Language.Haskell.TH.Syntax
 import Protocols
+import Protocols.Idle
 import Protocols.Wishbone
 
 import VexRiscv.ClockTicks
@@ -72,6 +73,10 @@ instance Protocol (Jtag dom) where
   type Fwd (Jtag dom) = Signal dom JtagIn
   type Bwd (Jtag dom) = Signal dom JtagOut
 
+instance IdleCircuit (Jtag dom) where
+  idleFwd _ = pure $ JtagIn 0 0 0
+  idleBwd _ = pure $ JtagOut 0 0
+
 vexRiscv ::
   forall dom .
   ( HasCallStack