move JTAG to its own domain

clash-lang · Oct 10, 2023 · fb88fb7 · fb88fb7
1 parent 23a74cf
commit fb88fb7
Show file tree

Hide file tree

Showing 7 changed files with 303 additions and 188 deletions.
diff --git a/clash-vexriscv-sim/app/HdlTest.hs b/clash-vexriscv-sim/app/HdlTest.hs
@@ -10,10 +10,14 @@ import VexRiscv
 circuit ::
   "CLK" ::: Clock System ->
   "RST" ::: Reset System ->
+  "TCK" ::: Clock System ->
   "INPUT" ::: Signal System Input ->
-  "OUTPUT" ::: Signal System Output
-circuit clk rst input =
-  withClockResetEnable clk rst enableGen vexRiscv input
+  "JTAG_IN_" ::: Signal System JtagIn ->
+  "" :::
+    ( "OUTPUT" ::: Signal System Output
+    , "JTAG_OUT_" ::: Signal System JtagOut)
+circuit clk rst tck input jtagIn =
+  vexRiscv clk rst tck enableGen input jtagIn
 
 makeTopEntity 'circuit
 

diff --git a/clash-vexriscv-sim/src/Utils/Cpu.hs b/clash-vexriscv-sim/src/Utils/Cpu.hs
@@ -27,8 +27,7 @@ emptyInput =
       externalInterrupt = low,
       softwareInterrupt = low,
       iBusWbS2M = (emptyWishboneS2M @(BitVector 32)) {readData = 0},
-      dBusWbS2M = (emptyWishboneS2M @(BitVector 32)) {readData = 0},
-      jtagIn = JtagIn { testModeSelect = low, testDataIn = low, testClock = low }
+      dBusWbS2M = (emptyWishboneS2M @(BitVector 32)) {readData = 0}
     }
 
 
@@ -54,12 +53,29 @@ cpu ::
   )
 cpu jtagPort bootIMem bootDMem = (output, writes, iS2M, dS2M)
   where
-    output = vexRiscv (emptyInput :- input)
+
+    {-
+vexRiscv ::
+  forall domCpu domJtag .
+  ( HasCallStack
+  , KnownDomain domCpu
+  , KnownDomain domJtag) =>
+  Clock domCpu ->
+  Reset domCpu ->
+  Clock domJtag ->
+  Enable domJtag ->
+  Signal domCpu Input ->
+  Signal domJtag JtagIn ->
+  ( Signal domCpu Output
+  , Signal domJtag JtagOut
+  )
+    -}
+    (output, jtagOut) = vexRiscv hasClock hasReset hasClock jtagEnable (emptyInput :- input) jtagIn
 
 
-    (jtagIn', _debugReset) = case jtagPort of
-      Just port -> unbundle $ unsafePerformIO $ jtagTcpBridge' (fromInteger port) hasReset (jtagOut <$> output)
-      Nothing -> (pure JTag.defaultIn, pure low)
+    (jtagEnable, jtagIn) = case jtagPort of
+      Just port -> unsafePerformIO $ jtagTcpBridge' (fromInteger port) jtagOut
+      Nothing -> (toEnable (pure False), pure JTag.defaultIn)
     -- (unbundle -> (jtagIn', _debugReset)) = unsafePerformIO $ jtagTcpBridge' 7894 hasReset (jtagOut <$> output) 
 
     dM2S = dBusWbM2S <$> output
@@ -80,19 +96,17 @@ cpu jtagPort bootIMem bootDMem = (output, writes, iS2M, dS2M)
       ((0x0000_0000, dummyS2M) :> (0x4000_0000, bootDS2M) :> Nil)
 
     input =
-      ( \iBus dBus jtagIn ->
+      ( \iBus dBus ->
           Input
             { timerInterrupt = low,
               externalInterrupt = low,
               softwareInterrupt = low,
               iBusWbS2M = makeDefined iBus,
-              dBusWbS2M = makeDefined dBus,
-              jtagIn = jtagIn
+              dBusWbS2M = makeDefined dBus
             }
       )
         <$> iS2M
         <*> dS2M
-        <*> jtagIn'
 
     unBusAddr = mapAddr ((`shiftL` 2) . extend @_ @_ @2)