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mediatek: filogic: update MT7988 device tree
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 * move ethernet to mt7988a.dtsi
 * move switch definition to mt7988a.dtsi
 * add PHY LEDs

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 64b9980)
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@dangowrt
dangowrt committed Aug 7, 2023
1 parent 830bb57 commit c072069
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241 changes: 87 additions & 154 deletions target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
/dts-v1/;
#include "mt7988a-rfb-spim-nand.dtsi"
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/leds/common.h>

/ {
model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
Expand All @@ -29,173 +30,105 @@
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
status = "okay";
};

gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "internal";
&gmac0 {
status = "okay";
};

fixed-link {
speed = <10000>;
full-duplex;
pause;
};
&gmac1 {
status = "okay";
phy-mode = "internal";
phy-connection-type = "internal";
phy = <&int_2p5g_phy>;
};

&gmac2 {
status = "okay";
phy-mode = "usxgmii";
phy-connection-type = "usxgmii";
phy = <&phy8>;
};

&mdio_bus {
/* external Aquantia AQR113C */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 72 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};

gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "internal";
phy-connection-type = "internal";
phy = <&phy15>;
/* external Aquantia AQR113C */
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 71 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};

gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
phy-mode = "10gbase-kr";
phy-connection-type = "10gbase-kr";
phy = <&phy8>;
/* external Maxlinear GPY211C */
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};

mdio0: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;

/* external Aquantia AQR113C */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 72 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};

/* external Aquantia AQR113C */
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 71 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};

/* external Maxlinear GPY211C */
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};

/* external Maxlinear GPY211C */
phy13: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};

/* internal 2.5G PHY */
phy15: ethernet-phy@15 {
reg = <15>;
pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "internal";
};
/* external Maxlinear GPY211C */
phy13: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};

&int_2p5g_phy {
pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
};

&switch {
status = "okay";
};

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
label = "lan0";
phy-mode = "internal";
phy-handle = <&gsw_phy0>;
};

port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&gsw_phy1>;
};

port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&gsw_phy2>;
};

port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&gsw_phy3>;
};

port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";

fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
&gsw_phy0 {
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe0_led0_pins>;
};

mdio {
#address-cells = <1>;
#size-cells = <0>;
mediatek,pio = <&pio>;

gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9481";
reg = <0>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe0_led0_pins>;
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
};

gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id03a2.9481";
reg = <1>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe1_led0_pins>;
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
};

gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id03a2.9481";
reg = <2>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe2_led0_pins>;
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
};

gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id03a2.9481";
reg = <3>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe3_led0_pins>;
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
};
};
&gsw_phy0_led0 {
status = "okay";
color = <LED_COLOR_ID_GREEN>;
};

&gsw_phy1 {
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe1_led0_pins>;
};

&gsw_phy1_led0 {
status = "okay";
color = <LED_COLOR_ID_GREEN>;
};

&gsw_phy2 {
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe2_led0_pins>;
};

&gsw_phy2_led0 {
status = "okay";
color = <LED_COLOR_ID_GREEN>;
};

&gsw_phy3 {
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe3_led0_pins>;
};

&gsw_phy3_led0 {
status = "okay";
color = <LED_COLOR_ID_GREEN>;
};
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