mediatek: fix PCIe #PERST being de-asserted too early

The driver for MediaTek gen3 PCIe hosts de-asserts all reset
signals at the same time using a single register write operation.
Delay the de-assertion of the #PERST signal by 100ms as some PCIe
devices fail to come up otherwise.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch

@@ -0,0 +1,17 @@
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -319,7 +319,13 @@ static int mtk_pcie_startup_port(struct
+ 	msleep(100);
+
+ 	/* De-assert reset signals */
+-	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
++	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
++	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
++
++	msleep(100);
++
++	/* De-assert PERST# signals */
++	val &= ~(PCIE_PE_RSTB);
+ 	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+ 	/* Check if the link is up or not */

target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch

@@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d
+@@ -1031,7 +1031,7 @@ static struct platform_driver mtk_pcie_d
  	.probe = mtk_pcie_probe,
  	.remove = mtk_pcie_remove,
  	.driver = {

target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch

@@ -0,0 +1,19 @@
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -350,9 +350,15 @@ static int mtk_pcie_startup_port(struct
+ 	msleep(100);
+
+ 	/* De-assert reset signals */
+-	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
++	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
+ 	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+
++	msleep(100);
++
++	/* De-assert PERST# signals */
++	val &= ~(PCIE_PE_RSTB);
++	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
++
+ 	/* Check if the link is up or not */
+ 	err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
+ 				 !!(val & PCIE_PORT_LINKUP), 20,