fix some sim build issues

.github/workflows/build.yml

@@ -35,7 +35,7 @@ jobs:
       - name: Configure for mips
         shell: bash
         run: |
-          ./configure --target=mips-linux --prefix=/opt/cross --disable-gprof --disable-werror --host=${{ matrix.TARGET.HOST }} --build=${{ matrix.TARGET.HOST }}
+          ./configure --target=mips-linux --prefix=/opt/cross --disable-werror --host=${{ matrix.TARGET.HOST }} --build=${{ matrix.TARGET.HOST }}
 
       - name: Make
         shell: bash
@@ -47,6 +47,9 @@ jobs:
           make -C gas CFLAGS="${{ matrix.TARGET.CFLAGS }}"
           make -C binutils CFLAGS="${{ matrix.TARGET.CFLAGS }}"
           make -C ld CFLAGS="${{ matrix.TARGET.CFLAGS }}"
+          make -C sim CFLAGS="${{ matrix.TARGET.CFLAGS }}"
+          make -C readline CFLAGS="${{ matrix.TARGET.CFLAGS }}"
+          make -C gdb CFLAGS="${{ matrix.TARGET.CFLAGS }}"
       - name: Test for file
         shell: bash
         run: |

.gitignore

@@ -103,3 +103,27 @@ gdb/testsuite/gdb.asm/arch.inc
 gdb/nm.h
 gdb/tm.h
 gdb/xm.h
+gdb/init.c
+gdb/version.c
+
+sim/igen/igen
+sim/mips/gentmap
+sim/mips/stamp-tvals
+sim/mips/targ-map.c
+sim/mips/targ-vals.h
+sim/mips/engine.c
+sim/mips/engine.h
+sim/mips/icache.c
+sim/mips/icache.h
+sim/mips/idecode.c
+sim/mips/idecode.h
+sim/mips/irun.c
+sim/mips/itable.c
+sim/mips/itable.h
+sim/mips/model.c
+sim/mips/model.h
+sim/mips/semantics.c
+sim/mips/semantics.h
+sim/mips/support.c
+sim/mips/support.h
+sim/mips/tmp-igen

sim/igen/gen-engine.c

@@ -98,21 +98,21 @@ print_run_body (lf *file,
   if (!options.gen.smp)
     {
 
-      lf_putstr (file, "
-/* CASE 1: NO SMP (with or with out instruction cache).
-
-In this case, we can take advantage of the fact that the current
-instruction address (CIA) does not need to be read from / written to
-the CPU object after the execution of an instruction.
-
-Instead, CIA is only saved when the main loop exits.  This occures
-when either sim_engine_halt or sim_engine_restart is called.  Both of
-these functions save the current instruction address before halting /
-restarting the simulator.
-
-As a variation, there may also be support for an instruction cracking
-cache. */
-
+      lf_putstr (file, "\
+/* CASE 1: NO SMP (with or with out instruction cache).\n\
+\n\
+In this case, we can take advantage of the fact that the current\n\
+instruction address (CIA) does not need to be read from / written to\n\
+the CPU object after the execution of an instruction.\n\
+\n\
+Instead, CIA is only saved when the main loop exits.  This occures\n\
+when either sim_engine_halt or sim_engine_restart is called.  Both of\n\
+these functions save the current instruction address before halting /\n\
+restarting the simulator.\n\
+\n\
+As a variation, there may also be support for an instruction cracking\n\
+cache. */\n\
+\n\
 ");
 
       lf_putstr (file, "\n");
@@ -215,14 +215,14 @@ cache. */
   if (options.gen.smp)
     {
 
-      lf_putstr (file, "
-/* CASE 2: SMP (With or without ICACHE)
-
-The complexity here comes from needing to correctly halt the simulator
-when it is aborted.  For instance, if cpu0 requests a restart then
-cpu1 will normally be the next cpu that is run.  Cpu0 being restarted
-after all the other CPU's and the event queue have been processed */
-
+      lf_putstr (file, "\
+/* CASE 2: SMP (With or without ICACHE)\n\
+\n\
+The complexity here comes from needing to correctly halt the simulator\n\
+when it is aborted.  For instance, if cpu0 requests a restart then\n\
+cpu1 will normally be the next cpu that is run.  Cpu0 being restarted\n\
+after all the other CPU's and the event queue have been processed */\n\
+\n\
 ");
 
       lf_putstr (file, "\n");

sim/igen/lf.c

@@ -259,27 +259,27 @@ lf_print__gnu_copyleft (lf *file)
   case lf_is_c:
   case lf_is_h:
     nr += lf_printf(file, "\
-/*  This file is part of the program psim.
-
-    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-    --
-
-    This file was generated by the program %s */
+/*  This file is part of the program psim.\n\
+\n\
+    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>\n\
+\n\
+    This program is free software; you can redistribute it and/or modify\n\
+    it under the terms of the GNU General Public License as published by\n\
+    the Free Software Foundation; either version 2 of the License, or\n\
+    (at your option) any later version.\n\
+\n\
+    This program is distributed in the hope that it will be useful,\n\
+    but WITHOUT ANY WARRANTY; without even the implied warranty of\n\
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n\
+    GNU General Public License for more details.\n\
+ \n\
+    You should have received a copy of the GNU General Public License\n\
+    along with this program; if not, write to the Free Software\n\
+    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n\
+ \n\
+    --\n\
+\n\
+    This file was generated by the program %s */\n\
 ", filter_filename(file->program));
     break;
   default: