decompals · Thar0 · Apr 28, 2024
diff --git a/include/PR/bbcard.h b/include/PR/bbcard.h
@@ -0,0 +1,35 @@
+#ifndef _BBCARD_H_
+#define _BBCARD_H_
+
+#include "ultratypes.h"
+#include "bbnand.h"
+
+#define BBCARD_ERR_NO_CARD	(-1)	/* no card present */
+#define BBCARD_ERR_FAIL		(-2)	/* operation failed */
+#define BBCARD_ERR_INVALID	(-3)	/* invalid parameters */
+#define BBCARD_ERR_CHANGED	(-4)	/* card changed */
+
+void osBbCardInit(void);
+s32 osBbCardReadBlock(u32 dev, u16 block, void* addr, void* spare);
+s32 osBbCardEraseBlock(u32 dev, u16 block);
+s32 osBbCardWriteBlock(u32 dev, u16 block, void* addr, void* spare);
+s32 osBbCardStatus(u32 dev, u8* status);
+s32 osBbCardChange(void);
+s32 osBbCardClearChange(void);
+u32 osBbCardBlocks(u32 dev);
+s32 osBbCardUnhappy(void);
+
+/* private */
+
+s32 __osBbCardGetAccess(void);
+void __osBbCardRelAccess(void);
+s32 __osBbCardWaitEvent(void);
+s32 __osBbCardFlushEvent(void);
+s32 __osBbCardPresent(void);
+
+extern u16 __osBbCardBlocks;
+extern u8 __osBbCardChange;
+extern u8 __osBbCardInit;
+extern u8 __osBbCardMultiplane;
+
+#endif
diff --git a/include/PR/bbfs.h b/include/PR/bbfs.h
@@ -1,10 +1,10 @@
-#ifndef BBFS_H_
-#define BBFS_H_
+#ifndef _BBFS_H_
+#define _BBFS_H_
 
 #include "ultratypes.h"
 
 #define BB_FL_BLOCK_SIZE	16384
-#define BB_INODE16_NAMELEN	11	/* maximum name length */
+#define BB_INODE16_NAMELEN	11	    /* maximum name length */
 #define BB_INODE16_NUM      409
 
 #define BBFS_ERR_NO_CARD    (-1)    /* card not present */
@@ -17,19 +17,37 @@
 #define BBFS_ERR_ENTRY      (-8)    /* no entry */
 
 /* Used for saving auxilliary game state data */
-#define BBFS_ERR_STATE          (-9)   /* invalid state */
-#define BBFS_ERR_STATE_LIMIT   (-10)   /* state limit reached */
+#define BBFS_ERR_STATE          (-9)    /* invalid state */
+#define BBFS_ERR_STATE_LIMIT   (-10)    /* state limit reached */
 
 typedef u16 BbFatEntry;
+#define BBFS_BLOCK_FREE     (0x0000)    /* block is available */
+#define BBFS_BLOCK_EOC      (0xFFFF)    /* indicates end-of-chain */
+#define BBFS_BLOCK_BAD      (0xFFFE)    /* indicates a bad block */
+#define BBFS_BLOCK_RESERVED (0xFFFD)    /* indicates system-reserved area */
+
+/**
+ * FS structure assuming 64MB NAND with 4096 blocks:
+ *  -    0 ..   63  SKSA
+ *  -   64 .. 4079  Data area
+ *  - 4080 .. 4095  BBFS FAT
+ */
+#define BBFS_SKSA_LIMIT 64  /* FIRST 64 blocks */
+#define BBFS_FAT_LIMIT  16  /* LAST 16 blocks */
 
 typedef struct {
-    /* 0x0000 */ u8 name[BB_INODE16_NAMELEN];
+    /* 0x0000 */ u8 name[BB_INODE16_NAMELEN]; // 8.3 name+extension format
     /* 0x000B */ u8 type;
-    /* 0x000C */ u16 block;
+    /* 0x000C */ u16 block; // first block in the chain belonging to this file
     /* 0x000E */ u16 pad;
     /* 0x0010 */ u32 size;
 } BbInode; // size = 0x14
 
+// `fat` is a `BbFat16` pointer
+#define BBFS_NEXT_BLOCK(fat, b) ((fat)[(b) >> 0xC].entry[(b) & 0xFFF])
+
+#define BBFS_CHECKSUM_VALUE (0xCAD7)
+
 typedef struct {
     /* 0x0000 */ BbFatEntry entry[4096];
     /* 0x2000 */ BbInode inode[BB_INODE16_NUM];
@@ -39,9 +57,6 @@ typedef struct {
     /* 0x3FFE */ u16 cksum;
 } BbFat16; // size = 0x4000
 
-// `fat` is a `BbFat16` pointer
-#define BBFS_NEXT_BLOCK(fat, b) (fat[b >> 0xC].entry[b & 0xFFF])
-
 extern BbFat16* __osBbFat;
 
 typedef struct {

diff --git a/include/PR/bbnand.h b/include/PR/bbnand.h
@@ -0,0 +1,127 @@
+#ifndef _BBNAND_H_
+#define _BBNAND_H_
+
+#define NAND_BYTES_PER_PAGE     0x200
+#define NAND_PAGE_SPARE_SIZE    0x10
+#define NAND_PAGES_PER_BLOCK    32
+#define NAND_BYTES_PER_BLOCK    (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE)
+
+#define NAND_BLOCK_TO_PAGE(blockNum) ((blockNum) * NAND_PAGES_PER_BLOCK)
+#define NAND_PAGE_TO_ADDR(pageNum) ((pageNum) * NAND_BYTES_PER_PAGE)
+#define NAND_BLOCK_TO_ADDR(pageNum) ((pageNum) * NAND_BYTES_PER_BLOCK)
+
+/* NAND Control (Read) */
+#define NAND_STATUS_BUSY        (1 << 31)
+#define NAND_STATUS_ERROR_DB    (1 << 10) /* Double-bit error, uncorrectable */
+#define NAND_STATUS_ERROR_SB    (1 << 11) /* Single-bit error, automatically corrected by ECC if enabled */
+
+/* NAND Control (Write) */
+/* Write 0 to PI_48_REG to clear flash interrupt */
+#define NAND_CTRL_CLR_INTR      0
+/* Other write bits */
+#define NAND_CTRL_EXEC         (1 << 31)     /* Execute NAND command immediately after write */
+#define NAND_CTRL_INTR         (1 << 30)     /* Interrupt when done */
+#define NAND_CTRL_UNK29        (1 << 29)
+#define NAND_CTRL_UNK28        (1 << 28)
+#define NAND_CTRL_UNK27        (1 << 27)
+#define NAND_CTRL_UNK26        (1 << 26)
+#define NAND_CTRL_UNK25        (1 << 25)
+#define NAND_CTRL_UNK24        (1 << 24)
+#define NAND_CTRL_CMD(cmd)     ((cmd) << 16) /* NAND command, sent directly to the NAND chip */
+#define NAND_CTRL_UNK15        (1 << 15)
+#define NAND_CTRL_BUFSEL(n)    ((n) << 14)   /* PI Buffer select, offset 0x000 or 0x200 */
+#define NAND_CTRL_DEVICE(n)    ((n) << 12)   /* NAND device select (2-bit) */
+#define NAND_CTRL_ECC          (1 << 11)     /* 1 if do ECC */
+#define NAND_CTRL_MULTICYCLE   (1 << 10)     /* 1 if NAND command is multicycle */
+#define NAND_CTRL_XFER_LEN(n)  ((n) << 0)    /* Transfer length in bytes between NAND and PI Buffer (10-bit) */
+
+/* NAND Command IDs */
+#define NAND_CMD_READ_0         0x00
+#define NAND_CMD_READ_1         0x01
+#define NAND_CMD_READ_2         0x50
+#define NAND_CMD_READ_ID        0x90
+#define NAND_CMD_RESET          0xFF
+#define NAND_CMD_FILL_PAGE      0x80
+#define NAND_CMD_WRITE_PAGE     0x10
+#define NAND_CMD_DUMMY_PAGE     0x11
+#define NAND_CMD_DUMMY_READ     0x03
+#define NAND_CMD_COPY_BACK      0x8A
+#define NAND_CMD_ERASE_PAGE     0x60
+#define NAND_CMD_EXEC_ERASE     0xD0
+#define NAND_CMD_READ_STATUS    0x70
+#define NAND_CMD_READ_STATUS_MP 0x71
+
+/* NAND Read Status (RSTAT) */
+
+#define NAND_RSTAT_ERASE_OK 0xC0
+
+/* NAND Read ID Response */
+
+#define NAND_ID_MULTIPLANE 0xC0
+
+#define NAND_ID_GET_MFG(status)        (((status) >> 0x18) & 0xFF)
+#define NAND_ID_GET_TYPE(status)       (((status) >> 0x10) & 0xFF)
+#define NAND_ID_IS_MULTIPLANE(status) ((((status) >> 0x00) & 0xFF) == NAND_ID_MULTIPLANE)
+
+/* NAND Command Macros */
+
+#define NAND_READ_0(nBytes, bufSelect, device, doEcc, intrDone)                               \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) |                                      \
+    NAND_CTRL_UNK28 | NAND_CTRL_UNK27 | NAND_CTRL_UNK26 | NAND_CTRL_UNK25 | NAND_CTRL_UNK24 | \
+    NAND_CTRL_CMD(NAND_CMD_READ_0) |                                                          \
+    NAND_CTRL_UNK15 | NAND_CTRL_BUFSEL(bufSelect) | NAND_CTRL_DEVICE(device) |                \
+    ((doEcc) ? NAND_CTRL_ECC : 0) | NAND_CTRL_XFER_LEN(nBytes))
+
+#define NAND_ERASE_PAGE(device, intrDone)                 \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) |  \
+    NAND_CTRL_UNK27 | NAND_CTRL_UNK26 | NAND_CTRL_UNK25 | \
+    NAND_CTRL_CMD(NAND_CMD_ERASE_PAGE) |                  \
+    NAND_CTRL_DEVICE(device) | NAND_CTRL_MULTICYCLE)
+
+#define NAND_EXEC_ERASE(device, intrDone)                \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) | \
+    NAND_CTRL_CMD(NAND_CMD_EXEC_ERASE) |                 \
+    NAND_CTRL_UNK15 | NAND_CTRL_DEVICE(device))
+
+#define NAND_READ_ID(bufSelect, device, intrDone)        \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) | \
+    NAND_CTRL_UNK28 | NAND_CTRL_UNK24 |                  \
+    NAND_CTRL_CMD(NAND_CMD_READ_ID) |                    \
+    NAND_CTRL_DEVICE(device) |                           \
+    NAND_CTRL_XFER_LEN(4))
+
+#define NAND_READ_STATUS(bufSelect, device, intrDone)        \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) |     \
+    NAND_CTRL_UNK28 |                                        \
+    NAND_CTRL_CMD(NAND_CMD_READ_STATUS) |                    \
+    NAND_CTRL_BUFSEL(bufSelect) | NAND_CTRL_DEVICE(device) | \
+    NAND_CTRL_XFER_LEN(1))
+
+#define NAND_READ_STATUS_CMD(cmd, bufSelect, device, intrDone) \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) |       \
+    NAND_CTRL_UNK28 |                                          \
+    NAND_CTRL_CMD(cmd) |                                       \
+    NAND_CTRL_BUFSEL(bufSelect) | NAND_CTRL_DEVICE(device) |   \
+    NAND_CTRL_XFER_LEN(1))
+
+#define NAND_FILL_PAGE(nBytes, bufSelect, device, doEcc, intrDone)                            \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) |                                      \
+    NAND_CTRL_UNK29 | NAND_CTRL_UNK27 | NAND_CTRL_UNK26 | NAND_CTRL_UNK25 | NAND_CTRL_UNK24 | \
+    NAND_CTRL_CMD(NAND_CMD_FILL_PAGE) |                                                       \
+    NAND_CTRL_BUFSEL(bufSelect) | NAND_CTRL_DEVICE(device) |                                  \
+    ((doEcc) ? NAND_CTRL_ECC : 0) | NAND_CTRL_MULTICYCLE | NAND_CTRL_XFER_LEN(nBytes))
+
+#define NAND_WRITE_PAGE(device, intrDone)                \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) | \
+    NAND_CTRL_CMD(NAND_CMD_WRITE_PAGE) |                 \
+    NAND_CTRL_UNK15 | NAND_CTRL_DEVICE(device))
+
+#define NAND_DUMMY_PAGE(device, intrDone)                \
+   (NAND_CTRL_EXEC | ((intrDone) ? NAND_CTRL_INTR : 0) | \
+    NAND_CTRL_CMD(NAND_CMD_DUMMY_PAGE) |                 \
+    NAND_CTRL_UNK15 | NAND_CTRL_DEVICE(device))
+
+/* Configuration with which to program PI_48_REG with when using ATB. */
+#define NAND_ATB_CONFIG(device, doEcc) (NAND_READ_0(0x3FF, 0, device, doEcc, FALSE) & ~NAND_CTRL_EXEC)
+
+#endif
diff --git a/include/PR/bcp.h b/include/PR/bcp.h
@@ -22,7 +22,6 @@
 #define MI_38_REG (MI_BASE_REG + 0x38)
 
 
-
 //! MI_HW_INTR_MASK_REG ?
 #define MI_3C_REG (MI_BASE_REG + 0x3C)
 
@@ -42,7 +41,18 @@
 
 
 
-//! PI_CARD_CNT_REG ?
+/**
+ *  [31]    : Exec
+ *  [30]    : Raise interrupt when command is done
+ *  [29:24] : ??
+ *  [23:16] : NAND command
+ *  [15]    : ??
+ *  [14]    : Buffer Select
+ *  [13:12] : Device Select
+ *  [11]    : ECC
+ *  [10]    : NAND command is multi-cycle
+ *  [ 9: 0] : Transfer Length
+ */
 #define PI_48_REG (PI_BASE_REG + 0x48)
 
 
@@ -88,8 +98,9 @@
 
 
 //! PI_EX_DMA_BUF ?
-#define PI_10000_REG(i) (PI_BASE_REG + 0x10000 + (i))
-
+#define PI_10000_BUF(offset)                    (PI_BASE_REG + 0x10000 + (offset))
+#define PI_NAND_DATA_BUFFER(bufSelect, offset)  PI_10000_BUF((bufSelect) * 0x200 + (offset))
+#define PI_NAND_SPARE_BUFFER(bufSelect, offset) PI_10000_BUF(0x400 + (bufSelect) * 0x10 + (offset))
 
 
 //! PI_ATB_LOWER_REG ?

diff --git a/src/bb/card/carderase.c b/src/bb/card/carderase.c
@@ -1,4 +1,5 @@
 #include "PR/os_internal.h"
+#include "PR/bbcard.h"
 #include "bcp.h"
 
 void __osBbCardRelAccess(void);
@@ -9,31 +10,31 @@ s32 __osBbCardStatus(u32 dev, u8* status, u32 buf);
 extern u8 __osBbCardMultiplane;
 
 static void erase_block(u32 dev, u32 addr) {
-    IO_WRITE(PI_70_REG, addr << 0xE);
-    IO_WRITE(PI_48_REG, (dev << 0xC) | 0x8E600400);
+    IO_WRITE(PI_70_REG, NAND_BLOCK_TO_ADDR(addr));
+    IO_WRITE(PI_48_REG, NAND_ERASE_PAGE(dev, FALSE));
 
     do {
         if (IO_READ(MI_38_REG) & 0x02000000) {
             return;
         }
-    } while (IO_READ(PI_48_REG) & 0x80000000);
+    } while (IO_READ(PI_48_REG) & NAND_STATUS_BUSY);
 
-    IO_WRITE(PI_48_REG, (dev << 0xC) | 0xC0D08000);
+    IO_WRITE(PI_48_REG, NAND_EXEC_ERASE(dev, TRUE));
 }
 
 static void erase_blocks(u32 dev, u16* addr, u32 n) {
     do {
-        IO_WRITE(PI_70_REG, addr[--n] << 0xE);
-        IO_WRITE(PI_48_REG, (dev << 0xC) | 0x8E600400);
+        IO_WRITE(PI_70_REG, NAND_BLOCK_TO_ADDR(addr[--n]));
+        IO_WRITE(PI_48_REG, NAND_ERASE_PAGE(dev, FALSE));
 
         do {
             if (IO_READ(MI_38_REG) & 0x02000000) {
                 return;
             }
-        } while (IO_READ(PI_48_REG) & 0x80000000);
+        } while (IO_READ(PI_48_REG) & NAND_STATUS_BUSY);
     } while (n != 0);
 
-    IO_WRITE(PI_48_REG, (dev << 0xC) | 0xC0D08000);
+    IO_WRITE(PI_48_REG, NAND_EXEC_ERASE(dev, TRUE));
 }
 
 s32 osBbCardEraseBlock(u32 dev, u16 block) {
@@ -47,10 +48,10 @@ s32 osBbCardEraseBlock(u32 dev, u16 block) {
 
     erase_block(dev, block);
     rv = __osBbCardWaitEvent();
-    if ((rv < 0) || __osBbCardStatus(dev, &tmp, 0) != 0) {
-        rv = -4;
-    } else if (tmp != 0xC0) {
-        rv = -2;
+    if (rv < 0 || __osBbCardStatus(dev, &tmp, 0) != 0) {
+        rv = BBCARD_ERR_CHANGED;
+    } else if (tmp != NAND_RSTAT_ERASE_OK) {
+        rv = BBCARD_ERR_FAIL;
     }
     __osBbCardRelAccess();
     return rv;
@@ -91,9 +92,9 @@ s32 osBbCardEraseBlocks(u32 dev, u16* block, u32 n) {
     }
 
     if (__osBbCardStatus(dev, &tmp, 0) != 0) {
-        rv = -4;
-    } else if (tmp != 0xC0) {
-        rv = -2;
+        rv = BBCARD_ERR_CHANGED;
+    } else if (tmp != NAND_RSTAT_ERASE_OK) {
+        rv = BBCARD_ERR_FAIL;
     }
 err:
     __osBbCardRelAccess();

diff --git a/src/bb/card/cardid.c b/src/bb/card/cardid.c
@@ -1,12 +1,6 @@
 #include "PR/os_internal.h"
 #include "PR/bcp.h"
-
-s32 __osBbCardGetAccess(void);
-void __osBbCardRelAccess(void);
-
-s32 __osBbCardWaitEvent(void);
-
-extern s8 __osBbCardMultiplane;
+#include "PR/bbcard.h"
 
 s32 osBbCardReadId(u32 dev, u32* mfg, u32* type) {
     u32 status;
@@ -18,13 +12,13 @@ s32 osBbCardReadId(u32 dev, u32* mfg, u32* type) {
     }
 
     IO_WRITE(PI_70_REG, 0);
-    IO_WRITE(PI_48_REG, (dev << 12) | 0xD1900004);
+    IO_WRITE(PI_48_REG, NAND_READ_ID(0, dev, TRUE));
 
     rv = __osBbCardWaitEvent();
-    status = IO_READ(PI_10000_REG(0));
-    *mfg = status >> 0x18;
-    *type = (status >> 0x10) & 0xFF;
-    __osBbCardMultiplane = (status & 0xFF) == 0xC0;
+    status = IO_READ(PI_NAND_DATA_BUFFER(0, 0));
+    *mfg = NAND_ID_GET_MFG(status);
+    *type = NAND_ID_GET_TYPE(status);
+    __osBbCardMultiplane = NAND_ID_IS_MULTIPLANE(status);
 
     __osBbCardRelAccess();
     return rv;