New: Finalize AXI-Crossbar integration and pass successfully the

compliance testsuite
dpretet · Dec 8, 2021 · e7a983e · e7a983e
1 parent c033857
commit e7a983e
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Showing 2 changed files with 7 additions and 5 deletions.
diff --git a/rtl/friscv_dcache.sv b/rtl/friscv_dcache.sv
@@ -166,6 +166,8 @@ module friscv_dcache
     ///////////////////////////////////////////////////////////////////////////
 
     // This FIFO stores the address for write data alignement 
+    // NB: UNUSED
+    // TODO: Evaluate if it could be needed
     friscv_scfifo 
     #(
     .PASS_THRU  (0),
@@ -206,7 +208,7 @@ module friscv_dcache
     // Write Data channel
     ///////////////////////////////////////////////////////////////////////////
 
-    assign wr_position = awaddr_w[ADDR_LSB+:SCALE_W];
+    assign wr_position = memfy_awaddr[ADDR_LSB+:SCALE_W];
 
     always @ (*) begin: GEN_WSTRB
         for (int i=0;i<SCALE;i=i+1) begin

diff --git a/test/common/axi4l_ram.sv b/test/common/axi4l_ram.sv
@@ -416,16 +416,16 @@ module axi4l_ram
                 p1_bvalid <= 1'b1;
                 p1_bid <= p1_awid_s;
 
-                if (AXI2_DATA_W<AXI_DATA_W) begin
-                    for (int i=0;i<AXI2_DATA_W/8;i++) begin
+                if (AXI1_DATA_W<AXI_DATA_W) begin
+                    for (int i=0;i<AXI1_DATA_W/8;i++) begin
                         if (p1_wstrb_s[i]) begin
                             mem[p1_awaddr_s[ADDR_LSB_W+:ADDRW]][(p1_wr_position+i*8)+:8] <= p1_wdata_s[8*i+:8];
                         end
                     end
                 end else begin
                     for (int i=0;i<AXI_DATA_W/8;i++) begin
                         if (p1_wstrb_s[i]) begin
-                            mem[p1_awaddr_s[ADDR_LSB_W+:ADDRW]][8*i+:8] <= p1_wdata[8*i+:8];
+                            mem[p1_awaddr_s[ADDR_LSB_W+:ADDRW]][8*i+:8] <= p1_wdata_s[8*i+:8];
                         end
                     end
                 end
@@ -475,7 +475,7 @@ module axi4l_ram
                 end else begin
                     for (int i=0;i<AXI_DATA_W/8;i++) begin
                         if (p2_wstrb_s[i]) begin
-                            mem[p2_awaddr_s[ADDR_LSB_W+:ADDRW]][8*i+:8] <= p2_wdata[8*i+:8];
+                            mem[p2_awaddr_s[ADDR_LSB_W+:ADDRW]][8*i+:8] <= p2_wdata_s[8*i+:8];
                         end
                     end
                 end