HDL Release 2

Fixed a few bugs that improved the quality of HDL SM83 implementation. Now something works even better there :-)
Also updated the wiki (sections on sequencer and ALU).

Some picture:

(shows core reset and the following INC A instruction flow)

Note: since the project is research in nature, just taking the HDL SM83 sources and aggregrating them into some other project may not work, but you can still try. It will be great if it ever works in hardware :-)

What's Changed

• Update DataLatch.v (hotfix) by @ogamespec in #201
• Get rid of clks by @ogamespec in #202
• Improved GekkioNames by @ogamespec in #205
• notes by @ogamespec in #206
• m1/poly topo without garbage by @ogamespec in #207
• Fixed bugs found by Verilator by @ogamespec in #208
• timescales by @ogamespec in #209
• Fixed bq7 typo by @ogamespec in #210
• Update Readme.md by @ogamespec in #212
• LoadIR port -> M1 by @ogamespec in #213
• Reverted PC to using w/x by @ogamespec in #215
• Use GekkioNames by @ogamespec in #216
• Cleaned up Seq by @ogamespec in #217
• Renamed some externals signals by @ogamespec in #218
• seq logisim wip by @ogamespec in #220
• logisim seq png by @ogamespec in #221
• fixed module4_2 by @ogamespec in #222
• Update seq_netlist.png by @ogamespec in #223
• polished seq logisim by @ogamespec in #224
• CLK2/1 for g84 by @ogamespec in #225
• Clarified use of CLK9/8 in seq dffs by @ogamespec in #227
• Update external_clk.v by @ogamespec in #228
• Fixed g84 CLK inputs by @ogamespec in #230
• HDL updated by @ogamespec in #231
• found missing DLatch (shifter result) by @ogamespec in #232
• Fight with ALU by @ogamespec in #233
• Update ALU.v by @ogamespec in #234
• ALU clarifications by @ogamespec in #235
• Fight with ALU continues by @ogamespec in #236
• Fixed azo8,9 in ALU (typo) by @ogamespec in #237

Full Changelog: hdl-first-release...hdl-release-2

NOP Engine

I think it's time to do some SM83 HDL release too.

After some fiddling and cross-checking with @Gekkio results (thanks a lot to him for the decoder dump!) - I managed to run the NOP instruction stream. You can see how the address bus increases its value after each M-cycle and something happens inside.

It needs some more tweaks and different tests, but I think it's something already.

You can find all the HDL source here: HDL

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Думаю что пора сделать тоже какой-то релиз SM83 HDL.

После некоторых пыхтений и сверок с результатами @Gekkio (большое ему спасибо за дамп декодера!) - удалось запустить поток инструкций NOP. Видно как адресная шина увеличивает свое значение после каждого M-цикла и внутри что-то происходит.

Нужно ещё немного подправить и сделать разные тесты, но думаю что это уже что-то.

Все исходники находятся тут: HDL

Topo Final

The tracing of all layers of the SM83 topology is completed.

Forever Link: https://github.com/emu-russia/dmgcpu/tree/main/imgstore/topo

Minor bugs may be corrected over time, but the critical mass is ready.

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Завершена трассировка всех слоев топологии SM83.

Вечная ссылка: https://github.com/emu-russia/dmgcpu/tree/main/imgstore/topo

Со временем могут быть исправлены мелкие недочёты, но критическая масса готова.

Topology 2.0

The SM83 topology has been worked out, and as a result we can already slowly move away from using microphotographs in favor of reconstructed topology. The bottom part is also worked out.

Проработана топология SM83, в результате чего можно уже потихоньку отходить от использования микрофотографий в пользу восстановленной топологии. Также проработана нижняя часть.

PSD Sources: https://drive.google.com/drive/u/2/folders/1deuhwmRb-PVv-K7pEllSLKQda2ft94Mk

VisualSim anyone?

Topology 1.0

The SM83 Core topology has been restored and all top connections have been identified. Using these results it is possible to obtain a schematic of the control parts of the processor.

Particularly much attention was paid to the Sequencer, since the public is mostly interested in it (all sorts of SLEEP Mode behavior).

The main goals of the research are accomplished:

• Getting pictures of the processor, including the transistor level. All datasets can be downloaded from datasets.md
• Identification of wires and blocks

I'm done with the research for now, I need to rest and regroup. If anything, ask questions in the Discussions section.

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Выполнено восстановление топологии SM83 Core и идентифицированы все соединения верхней части. Используя эти результаты можно получить схему управляющих частей процессора.

Особенно много внимания было уделено Sequencer, т.к. общественность интересуется по большей части именно им (всякие особенности поведения SLEEP Mode).

Основные цели исследования выполнены:

• Получение фотографий процессора, в том числе уровня транзисторов. Все датасеты можно скачать из раздела datasets.md
• Идентификация проводов и блоков

Я пока закончил с исследованием, нужно отдохнуть и перегруппироваться. Если что, задавайте вопросы в разделе Discussions.