LiteEthMAC: remove logic loop in hybrid mode #115
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The hardware and cpu ports' valid signals can not be made dependent on their own ready signals, since this creates combinatorial loops. This should be unnecessary anyway though, the only thing that matters is that the valid signal is not asserted while the other sink is not ready.
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I haven't had time to actualy test this yet, so I'll keep it a draft for now unless you're sure this is correct. |
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Thanks @Xiretza, I'll study it in the next days. |
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The hardware and cpu ports' valid signals can not be made dependent on their own ready signals, since this creates combinatorial loops. This should be unnecessary anyway though, the only thing that matters is that the valid signal is not asserted while the other sink is not ready.