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Draft verilog generators #122

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Draft verilog generators #122

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Commits on Nov 4, 2022

  1. refactor core and add Etherbone (NOTE: nothing tested)

    @suarezvictor
    suarezvictor committed Nov 4, 2022
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Commits on Nov 5, 2022

  1. add support for simulation phy and etherbone core generation

    @suarezvictor
    suarezvictor committed Nov 5, 2022
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  2. add .yml example configuration files

    @suarezvictor
    suarezvictor committed Nov 5, 2022
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  3. fixed master interface in generator, added WB slave adaptation like i… 

    …n LiteSPI (same code but not tested yet)
    @suarezvictor
    suarezvictor committed Nov 5, 2022
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  4. fix bug in etherbone (now works in simulation)

    @suarezvictor
    suarezvictor committed Nov 5, 2022
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Commits on Nov 6, 2022

  1. add config for axi-lite in simulation

    @suarezvictor
    suarezvictor committed Nov 6, 2022
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