arm: armv7-a/r and armv8-r up_cpu_index inline

reason:
inline small code to improve performance

Signed-off-by: hujun5 <hujun5@xiaomi.com>

arch/arm/include/arm/irq.h

@@ -219,6 +219,29 @@ static inline irqstate_t up_irq_enable(void)
      : "cc", "memory");
   return flags;
 }
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void) noinstrument_function;
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 #endif /* __ASSEMBLY__ */
 
 /****************************************************************************

arch/arm/include/armv6-m/irq.h

@@ -331,6 +331,28 @@ static inline void setcontrol(uint32_t control)
       : "memory");
 }
 
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void) noinstrument_function;
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 static inline_function uint32_t up_getsp(void)
 {
   register uint32_t sp;

arch/arm/include/armv7-a/irq.h

@@ -198,6 +198,20 @@
 
 #define REG_PIC             REG_R10
 
+/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
+
+#define MPIDR_CPUID_SHIFT   (0)       /* Bits 0-1: CPU ID */
+#define MPIDR_CPUID_MASK    (3 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU0  (0 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU1  (1 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU2  (2 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU3  (3 << MPIDR_CPUID_SHIFT)
+                                      /* Bits 2-7: Reserved */
+#define MPIDR_CLUSTID_SHIFT (8)       /* Bits 8-11: Cluster ID value */
+#define MPIDR_CLUSTID_MASK  (15 << MPIDR_CLUSTID_SHIFT)
+                                      /* Bits 12-29: Reserved */
+#define MPIDR_U             (1 << 30) /* Bit 30: Multiprocessing Extensions. */
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -425,6 +439,44 @@ noinstrument_function static inline void up_irq_restore(irqstate_t flags)
     );
 }
 
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+noinstrument_function
+static inline_function int up_cpu_index(void)
+{
+  unsigned int mpidr;
+
+  /* Read the Multiprocessor Affinity Register (MPIDR) */
+
+  __asm__ __volatile__
+  (
+    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
+    : "=r"(mpidr)
+  );
+
+  /* And return the CPU ID field */
+
+  return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
+}
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 static inline_function uint32_t up_getsp(void)
 {
   register uint32_t sp;

arch/arm/include/armv7-m/irq.h

@@ -536,6 +536,28 @@ static inline void setcontrol(uint32_t control)
       : "memory");
 }
 
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void) noinstrument_function;
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 static inline_function uint32_t up_getsp(void)
 {
   register uint32_t sp;

arch/arm/include/armv7-r/irq.h

@@ -198,6 +198,20 @@
 
 #define REG_PIC             REG_R10
 
+/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
+
+#define MPIDR_CPUID_SHIFT   (0)       /* Bits 0-1: CPU ID */
+#define MPIDR_CPUID_MASK    (3 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU0  (0 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU1  (1 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU2  (2 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU3  (3 << MPIDR_CPUID_SHIFT)
+                                      /* Bits 2-7: Reserved */
+#define MPIDR_CLUSTID_SHIFT (8)       /* Bits 8-11: Cluster ID value */
+#define MPIDR_CLUSTID_MASK  (15 << MPIDR_CLUSTID_SHIFT)
+                                      /* Bits 12-29: Reserved */
+#define MPIDR_U             (1 << 30) /* Bit 30: Multiprocessing Extensions. */
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -420,6 +434,44 @@ static inline void up_irq_restore(irqstate_t flags)
     );
 }
 
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+noinstrument_function
+static inline_function int up_cpu_index(void)
+{
+  uint32_t mpidr;
+
+  /* Read the Multiprocessor Affinity Register (MPIDR) */
+
+  __asm__ __volatile__
+  (
+    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
+    : "=r"(mpidr)
+  );
+
+  /* And return the CPU ID field */
+
+  return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
+}
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 static inline_function uint32_t up_getsp(void)
 {
   register uint32_t sp;

arch/arm/include/armv8-m/irq.h

@@ -509,6 +509,28 @@ static inline void setcontrol(uint32_t control)
       : "memory");
 }
 
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void) noinstrument_function;
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 static inline_function uint32_t up_getsp(void)
 {
   uint32_t sp;

arch/arm/include/armv8-r/irq.h

@@ -198,6 +198,20 @@
 
 #define REG_PIC             REG_R10
 
+/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
+
+#define MPIDR_CPUID_SHIFT   (0)       /* Bits 0-1: CPU ID */
+#define MPIDR_CPUID_MASK    (3 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU0  (0 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU1  (1 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU2  (2 << MPIDR_CPUID_SHIFT)
+#  define MPIDR_CPUID_CPU3  (3 << MPIDR_CPUID_SHIFT)
+                                      /* Bits 2-7: Reserved */
+#define MPIDR_CLUSTID_SHIFT (8)       /* Bits 8-11: Cluster ID value */
+#define MPIDR_CLUSTID_MASK  (15 << MPIDR_CLUSTID_SHIFT)
+                                      /* Bits 12-29: Reserved */
+#define MPIDR_U             (1 << 30) /* Bit 30: Multiprocessing Extensions. */
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -420,6 +434,44 @@ static inline void up_irq_restore(irqstate_t flags)
     );
 }
 
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+noinstrument_function
+static inline_function int up_cpu_index(void)
+{
+  uint32_t mpidr;
+
+  /* Read the Multiprocessor Affinity Register (MPIDR) */
+
+  __asm__ __volatile__
+  (
+    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
+    : "=r"(mpidr)
+  );
+
+  /* And return the CPU ID field */
+
+  return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
+}
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 static inline_function uint32_t up_getsp(void)
 {
   register uint32_t sp;

arch/arm/include/tlsr82/irq.h

@@ -236,6 +236,28 @@ static inline uint32_t getcontrol(void)
   return 0;
 }
 
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void) noinstrument_function;
+#else
+#  define up_cpu_index() 0
+#endif /* CONFIG_SMP */
+
 static inline_function uint32_t up_getsp(void)
 {
   register uint32_t sp;

arch/arm/src/armv7-a/CMakeLists.txt

@@ -105,14 +105,7 @@ if(CONFIG_ARCH_FPU)
 endif()
 
 if(CONFIG_SMP)
-  list(
-    APPEND
-    SRCS
-    arm_cpuindex.c
-    arm_cpustart.c
-    arm_cpupause.c
-    arm_cpuidlestack.c
-    arm_scu.c)
+  list(APPEND SRCS arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c arm_scu.c)
 endif()
 
 if(CONFIG_ARCH_HAVE_PSCI)

arch/arm/src/armv7-a/Make.defs

@@ -90,7 +90,7 @@ ifeq ($(CONFIG_ARCH_FPU),y)
 endif
 
 ifeq ($(CONFIG_SMP),y)
-  CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
+  CMN_CSRCS += arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
   CMN_CSRCS += arm_scu.c
 endif