doc updates

intel · Nov 25, 2024 · 0aac3f6 · 0aac3f6
1 parent 36cf059
commit 0aac3f6
Show file tree

Hide file tree

Showing 2 changed files with 12 additions and 1 deletion.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,6 +1,6 @@
 ## Next release
 
-- Added `LogicNet`, `inOut`s, and `TriStateBuffer` to enable multi-directional wires, ports, and drivers.
+- Added `LogicNet`, `inOut`s, and `TriStateBuffer` to enable multi-directional wires, ports, and drivers. Includes support for "wire-only" operations supporting multiple drivers.
 - Deprecated `CustomSystemVerilog` in favor of `SystemVerilog`, which has similar functionality but supports `inOut` ports, and collapses all ports into a single `ports` argument, as well as some other new features like custom definitions and parameter passthroughs.
 - Breaking: `ExternalSystemVerilogModule` and `InlineSystemVerilog` now extend `SystemVerilog` instead of `CustomSystemVerilog`, meaning the `instantiationVerilog` API arguments have been modified.
 - Breaking: Increased minimum Dart SDK version to 3.0.0.

diff --git a/doc/user_guide/_docs/A22-logic-nets.md b/doc/user_guide/_docs/A22-logic-nets.md
@@ -39,3 +39,14 @@ class ModWithInout extends Module {
   }
 }
 ```
+
+## Subsets, Swizzles, and More with Logic Nets
+
+Any operation on `LogicNet`s which does not imply any logic other than just wire connectivity will behave bidirectionally.  Some examples include:
+
+- Subsets (`getRange`, `slice`, etc.)
+- Swizzling
+- Shifts by constant amounts
+- Reversing
+- Zero and sign extension
+- Replication