Add support for SystemVerilog parameter passthroughs

[mkorbel1]

Description & Motivation

Even though SystemVerilog parameters are not supported for controlling anything within generated outputs of SystemVerilog, sometimes there is a need to pass parameters down through a ROHD-generated hierarchy into ExternalSystemVerilog modules. This PR provides that capability.

Related Issue(s)

N/A

Testing

Added new tests, plus existing tests

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

Yes!

The API for SystemVerilog has changed, including default behavior. This PR occurs between releases, however, so this is not a delta over previous releases since no release yet has SystemVerilog. This may impact people pointing at main.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Not really any user guide stuff, the documentation on advanced features is not very deep and refers to the API docs, which were updated.