Allow LogicNets to bidirectionally drive operations which are just wires

[mkorbel1]

Description & Motivation

There are numerous operations on signals which in reality only represent wires. For example:

• Subsets
• Swizzles
• Shifts by constants amounts
• Reversing
• Zero/sign extending
• Replicating

Since there's no real logic on the path, it makes sense for LogicNets to support bidirectional driving across these gates. Additionally, some things (especially subsets and swizzles) are crucial for useful routing of LogicNet signals for connectivity -- otherwise only full-bus could be used effectively.

This PR introduces changes so that LogicNets can have bidirectional driving through these gates. It also fixes SystemVerilog generation so that the SV matches the behavior of the ROHD simulator with these new features.

Some other misc changes:

• Const constructor updated so width is more intuitive.
• Improved "unassignable" errors and marked more things as unassignable that should be.

Related Issue(s)

Fix #518
Defer #530 to later (prettier SV)

Testing

Added extensive testing for new functionality.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

• Behavior of LogicNets has changed, but it was arguably broken before, and not released previously (yet).
• Const constructor updated so that specified width takes precedence over the inherent width of a provided LogicValue val.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Updated user guide and CHANGELOG, in addition to the usual API doc updates.