This repository contains test suites based on Verilog and SystemVerilog standards.
The owner is Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS).
You may contribute to this repository by submitting pull requests and by commenting on pull requests submitted by other people. A pull request will be merged when a concensus/decision has been reached by maintainers.
For more information, please contact microtesk-support@ispras.ru.