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Faculty of Technical Sciences, Novi Sad
- Zrenjanin
Pinned Loading
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RISCV_multicore_cache_controller
RISCV_multicore_cache_controller PublicThis project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.
SystemVerilog 3
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UVM-Verification-of-CNN-hardware-accelerator
UVM-Verification-of-CNN-hardware-accelerator PublicDeo veceg projekta koji je iskoriscen za diplomski rad.
SystemVerilog 1
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Fault-Tolerant-FIR-projekat
Fault-Tolerant-FIR-projekat PublicProjekat iz predmeta "Digitalni sistemi otporni na greške", master akademske studije
VHDL 1
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Pacman-projekat
Pacman-projekat PublicDrugi zadatak iz predmeta "Multiprocesorski sistemi", master akademske studije
C++ 1
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Fox-and-Geese-Android-projekat
Fox-and-Geese-Android-projekat PublicTreci zadatak iz predmeta "Razvoj softvera za embeded operativne sisteme", master akademske studije
Java 1
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MusicLibraryDB-Android-projekat
MusicLibraryDB-Android-projekat PublicČetvrti zadatak iz predmeta "Razvoj softvera za embeded operativne sisteme", master akademske studije
Java 1
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