Listen Mode on Preamble wake up FSK sequencer on RFM95W

[pikkuri14]

Is there someone that successfully do the listen mode concept? Right now, I'm only able to make the rfm95w to go sleep and receive at a defined time using the sequencer, but still can't detect the preamble.

I've set the idle timer to 10s and receiver timer to 3s, and on the transmitter side, I sent the packet every 500ms delay, that the receiver side should be able to receive, right? but it still can't detect anything.

[jgromes]

Personally I have not used this feature on the RFM9x/SX127x, as it was always easier to just keep the device in Rx mode. This is also why there's basically no support for this in the SX127x driver, it's just very rarely used.

[pikkuri14]

I don't use startReceive as I only want to detect the preamble interrupt so far. I have a finding that i failed to write on the start bit register

int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SX127X_REG_SEQ_CONFIG_1, RADIOLIB_SX127X_SEQUENCER_START, 7,7);

it returns -16, what I confused about is why is it only that specific bit that failed to be written, and the cycle/timer that changes state of the module that I was expecting is ran as expected

[jgromes]

The SPI check can fail due to bad timing if it takes a bit of extra time for teh register to update after the value has been written to it. You can experiment with the checkInterval and checkMask arguments of SPIsetRegValue. Sometimes it helps to make the check interval longer than the default 2 ms. If that doesn't resolve and if you are sure that the required change really takes effect, you can suppress checking of that specific bit by removing it from the check mask, i.e. checkMask = 0x7F.

[pikkuri14]

well, it's actually written on the datasheet that both of start and stop bit are Write-triggered and always reads back as 0, that's why it was detected as error. That means yea, my TLS is running. Back to the main problem, what are the things that possibly make RFM95W can't outputs onPreambleDetect interrupts?

[jgromes]

both of start and stop bit are Write-triggered and always reads back as 0, that's why it was detected as error

That indeed explains it - I never used those bits so I never had this issue. It might be easier to use SPIwriteRegister as opposed to set value, depending on whether there are any additional bits that need to be guarded.

Unfortunately I can't really help you with much beyond that, sorry :/ The approach I would take would be to try to figure out whether this is because the preamble not being detected (e.g. by periodically reading some register) or whether this the signal is not being routed to the DIO pin.

[pikkuri14]

I have read the IRQ register periodically.

1. In FSK non-TLS mode, there is no change in preamble bit, instead the syncWord and payloadReady bit are (message received successfully).
2. in FSK TLS mode, there are no changes at all in those bits.

in the non-TLS, there is startReceive() where I can't quite following the code especially in the IRQ section (my first time dealing with register and bitwise operation/manipulation). my plan is changed, the TLS need to detect the syncWord, maybe could you help me understand to configure the IRQ setting? so that I can write that before I start the sequencer.

As far as I know, IRQ behaves by itself right? we don't need setting anything except the IRQ flag change will be mapped to which DIO, is that right?

Also I have a finding, where I read the IRQ register, it shows that FIFO is always full.