ASIC-Implementation-of-CV32E40S-RISC-V-core-

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR) ,using industry-leading tools such as Synopsys Design Compiler and ICC2.

Integration with PULPino SoC

In addition to the ASIC implementation of the RISC-V core, this project involves the integration of the designed core into the PULPino System-on-Chip (SoC). This step ensures that the high-performance RISC-V core is effectively utilized within a larger system context, enhancing its versatility and applicability.

Acknowledgments

Special thanks to Prof. Hani Fikry for guidance and Icpedia Company for sponsorship.