This bridge implements a simple converter to connect compact JTAG (cJTAG) probes to IEEE 1149.1 4-wire JTAG device. cJTAG only uses two wires: a uni-directional clock generated by the probe (TCKC) and a bi-directional data signal (TMSC).
ℹ️ This bridge only supports the OScan1 cJTAG format yet.
Origianl VHDL code from cjtag_bridge, convert it to Verilog file, and using Verilator for simulation.
The top entity is rtl/cjtag_bridge.v:
module cjtag_bridge (
// global control
input clk_i, // main clock
input rstn_i, // main reset, async, low-active
// cJTAG (from debug probe)
input tckc_i, // tap clock
input tmsc_i, // tap data input
output tmsc_o, // tap data output
output tmsc_oe_o, // tap data output enable (tri-state driver)
// JTAG (to device)
output tck_o, // tap clock
output tdi_o, // tap data input
input tdo_i, // tap data input
output tms_o, // tap mode select
// Debugging (for testing only)
output db_tck_rising_o,
output db_tck_falling_o
);ℹ️ The cJTAG clock frequency (TCKC signal) must not exceed 1/5 of the main clock (clk_i signal) frequency.
ℹ️ All 4-wire JTAG signals are expected to be sync to clk_i (same clock domain).
ℹ️ The debug signals db_* are intended for testing/development only.
The bridge requires a module-external tri-state driver for the off-chip TMSC signal (tmsc), which handles the module's
tmsc_i, tmsc_o and tmsc_oe_o signals:
The projects provides a very simple testbench to test the basic IO functions
(sim/cjtag_bridge_tb.v).
It can be simulated by Verilator via the Makefile
cjtag_bridge/sim$ make
The simulation will run for 1ms using a 100MHz clock. The waveform data is stored to sim/wave.fst
so it can be viewed using gtkwave:
cjtag_bridge/sim$ gtkwave wave.fst
🚧 TODO 🚧