verilog this is a project with verilog in "ISE design suite 14.7" the FPGA model is : xc6sslx9-3tqg144
and modules are:
1: set_pc : do one_bit_adder and rest with push_buttons (8 bit) 2:LED : show 16 bit in LED on fpga 3:dip_swich : get 16 bit from dip switches on fpga and 5 bit from push buttons 4:decoder : get 16 bit and chang to one "8 bit" and two "4 bit" 5:reg_bank:it`s a register bank with "case" that get a "4bit" address and give "16bit" in out put 6:execute:do sum and minus with two "16 bit" and give "16 bit" in out put 7:seven segment:to show "4bit" in seven segment 8:first.ucf: need for fpga 9:top:the main module 10:push_button:just for push button
good luck...
mohammad-hassani