Contains reverse engineered schematics of the Game Boy DMG-CPU B chip.
The schematics in this repository are derived from the schematics in furrtek/DMG-CPU-Inside (CC-BY-SA 4.0 Furrtek).
Most recent PDF export can be found here, or in the release section on github.
| File(s) | Description |
|---|---|
| ./dmg_cpu_b/dmg_cpu_b.kicad_pro | KiCad project file for the schematics of the chip. |
| ./dmg_cpu_b/*.kicad_sch | KiCad schematic sheets. |
| ./dmg_cpu_b/lib/DMG_CPU_Cells.kicad_sym | KiCad library with symbols for all the logic cells in the chip. |
| ./dmg_cpu_b/overlay/dmg-cpu-b_overlay.svg | Modified version of Furrtek's overlay for the chip's die shot. |
| ./dmg_cells/dmg-cpu.jelib | Electric VLSI cell library containing layouts of the cells used in the chip. |
| ./netlist/*.nl | Text files containing all cells and wires, and their connections and coordinates. |
The overlay SVG image contains the contours of the cells in the die shot and highlights all the wires connecting the cells. Also the cells are labeled with the same names they have in the schematics.
We took the overlay from Furrtek and modified it to keep it in sync with the fixed schematics.
To open the overlay with a SVG viewer/editor (like Inkscape) you need to download the die shots and place them into the same directory where the overlay file is. The die shots can be downloaded from here and here.
The Electric VLSI library contains layouts and schematics for the standard cells used in the chip.
Screenshots of these layouts can be seen in the cell reference documentation here.
The files in the netlist folder contain definitions for all cells and wires of the chip. They can be parsed by the nlconv tool. This tool is currently capable of converting the netlists into the following products:
- HTML file with colors and links that make the netlists more readable.
- PNG images that are used for the overlays on the Leaflet map of the chip.
- Java Script code that is used by the same Leaflet map for allowing the user to click on and select cells and wires, to get more information about them.
It is planned to add the functionality to generate HDL code for simulation from the same files.