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Added x86 'sm3/sm4' detection (#127)
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whyb authored Oct 14, 2024
1 parent b9a2faf commit 0edcf26
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4 changes: 2 additions & 2 deletions README.md
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Expand Up @@ -62,7 +62,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._

|CPU|ISA|
|:---:|---|
|x86|`mmx` `sse` `sse2` `sse3` `ssse3` `sse41` `sse42` `sse4a` `xop` `avx` `f16c` `fma` `fma4` `avx2` `avx512f` `avx512bw` `avx512cd` `avx512dq` `avx512vl` `avx512vnni` `avx512bf16` `avx512ifma` `avx512vbmi` `avx512vbmi2` `avx512fp16` `avx512er` `avx5124fmaps` `avx5124vnniw` `avxvnni` `avxvnniint8` `avxvnniint16` `avxifma` `amxfp16` `amxbf16` `amxint8` `amxtile` `bmi1` `bmi2` `gfni` `aesni` `vaes` `sha` `rdrand` `rdseed` `tsx`|
|x86|`mmx` `sse` `sse2` `sse3` `ssse3` `sse41` `sse42` `sse4a` `xop` `avx` `f16c` `fma` `fma4` `avx2` `avx512f` `avx512bw` `avx512cd` `avx512dq` `avx512vl` `avx512vnni` `avx512bf16` `avx512ifma` `avx512vbmi` `avx512vbmi2` `avx512fp16` `avx512er` `avx5124fmaps` `avx5124vnniw` `avxvnni` `avxvnniint8` `avxvnniint16` `avxifma` `amxfp16` `amxbf16` `amxint8` `amxtile` `bmi1` `bmi2` `gfni` `aesni` `vaes` `sha` `sm3` `sm4` `rdrand` `rdseed` `tsx`|
|arm|`half` `edsp` `neon` `vfpv4` `idiv`|
|aarch64|`neon` `vfpv4` `lse` `cpuid` `asimdrdm` `asimdhp` `asimddp` `asimdfhm` `bf16` `i8mm` `frint` `jscvt` `fcma` `mte` `mte2` `sve` `sve2` `svebf16` `svei8mm` `svef32mm` `svef64mm` `sme` `smef16f16` `smef64f64` `smei64i64` `pmull` `crc32` `aes` `sha1` `sha2` `sha3` `sha512` `sm3` `sm4` `svepmull` `svebitperm` `sveaes` `svesha3` `svesm4` `amx`|
|mips|`msa` `mmi` `sx` `asx` `msa2` `crypto`|
Expand Down Expand Up @@ -784,7 +784,7 @@ ruapu determines whether the CPU supports certain instruction sets by trying to
* [@dreamcmi](https://github.com/dreamcmi)  _Detect more risc-v ISA_
* [@cocoa-xu](https://github.com/cocoa-xu)  _Add FreeBSD support, python support_
* [@YuzukiTsuru](https://github.com/YuzukiTsuru)  _Add OpenRISC support_
* [@whyb](https://github.com/whyb)  _Detect x86 AMX_
* [@whyb](https://github.com/whyb)  _Detect more x86 AMX*, SHA*, AVX512*, SM*_

## License
MIT License
2 changes: 2 additions & 0 deletions main.c
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Expand Up @@ -58,6 +58,8 @@ int main()
PRINT_ISA_SUPPORT(aesni)
PRINT_ISA_SUPPORT(vaes)
PRINT_ISA_SUPPORT(sha)
PRINT_ISA_SUPPORT(sm3)
PRINT_ISA_SUPPORT(sm4)
PRINT_ISA_SUPPORT(rdrand)
PRINT_ISA_SUPPORT(rdseed)
PRINT_ISA_SUPPORT(tsx)
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4 changes: 4 additions & 0 deletions ruapu.h
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Expand Up @@ -231,6 +231,8 @@ RUAPU_INSTCODE(gfni, 0x66, 0x0f, 0x38, 0xcf, 0xc0) // gf2p8mulb xmm0,xmm0
RUAPU_INSTCODE(aesni, 0x66, 0x0f, 0x38, 0xdc, 0xc0) // aesenc xmm0,xmm0
RUAPU_INSTCODE(vaes, 0xc4, 0xe2, 0x7d, 0xdc, 0xc0) // vaesenc ymm0,ymm0,ymm0
RUAPU_INSTCODE(sha, 0x0f, 0x38, 0xc9, 0xc0) // sha1msg1 xmm0,xmm0
RUAPU_INSTCODE(sm3, 0xc4, 0xe2, 0x78, 0xda, 0xc0) // vsm3msg1 xmm0,xmm0,xmm0
RUAPU_INSTCODE(sm4, 0xc4, 0xe2, 0x7e, 0xda, 0xc0) // vsm4key4 ymm0,ymm0,ymm0
RUAPU_INSTCODE(rdrand, 0x0f, 0xc7, 0xf0) // rdrand eax
RUAPU_INSTCODE(rdseed, 0x0f, 0xc7, 0xf8) // rdseed eax
RUAPU_INSTCODE(tsx, 0x0f, 0x01, 0xd6) // xtest
Expand Down Expand Up @@ -451,6 +453,8 @@ RUAPU_ISAENTRY(gfni)
RUAPU_ISAENTRY(aesni)
RUAPU_ISAENTRY(vaes)
RUAPU_ISAENTRY(sha)
RUAPU_ISAENTRY(sm3)
RUAPU_ISAENTRY(sm4)
RUAPU_ISAENTRY(rdrand)
RUAPU_ISAENTRY(rdseed)
RUAPU_ISAENTRY(tsx)
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