RV32I

An RV32I core implementation

Requirements

• Icicle
• Docker
• (Optional) VSCode

Directories

• rtl - HDL sources and RTL level code required to implement the design
• sdk - Accompanying software/firmware
• sim - Simulation sources used to validate the HDL sources
• board - Board supporting configuration files, including constraints and build parameters
• mem - Memory initialization files

Usage

RTL

The toolchain can be installed and activated using icicle.

$ icicle install
$ icicle use

The project is built using make. The root Makefile has a handy help target which documents commands available

$ make help
all                            Run sys, pnr and bitstream generation for the given BOARD
clean                          Deletes and recreates the build folder
help                           Print this help message
program                        Program the given BOARD

You can configure the target board by updating the BOARD variable in the Makefile

- BOARD ?= icesugar
+ BOARD ?= alchitry_cu

or by providing it as a variable when running a target.

$ make all BOARD=alchitry_cu 

You can add and remove your own board configurations in the board folder by adding

make 

SDK

SDK sources are compiled using the RISC-V GCC. A handy Dockerfile is provided in the sdk folder and can be used to build an image with the required tooling.

$ cd sdk
$ docker build -t rvgcc .

This will build and tag the image as rvgcc. You can create a container and access the shell using

docker run -it --entrypoint=/bin/bash rvgcc

To mount the project to a directory within the container you can use -v.

docker run -it -v $PWD:/sdk --entrypoint=/bin/bash rvgcc

Supported Instructions

• lui
• auipc
• addi
• slti
• sltiu
• xori
• ori
• andi
• slli
• srli
• srai
• add
• sub
• sll
• slt
• sltu
• xor
• srl
• sra
• or
• and
• fence
• csrrw
• csrrs
• csrrc
• csrrwi
• csrrsi
• csrrci
• ecall
• ebreak
• uret
• sret
• mret
• wfi
• lb
• lh
• lw
• lbu
• lhu
• sb
• sh
• sw
• jal
• jalr
• beq
• bne
• blt
• bge
• bltu
• bgeu

Resources

• The RISC-V Instruction Set Manual. Volume I: User-Level ISA
• RISC-V Assembly Programmer's Manual
• RISC-V Online Assembler
• RISC-V Online Interpreter
• RISC-V Instruction Encoder/Decoder
• RISC-V GNU Compiler Toolchain
• RISC-V ISA base and extensions
• UART Design and Programming
• The -march, -mabi, and -mtune arguments to RISC-V Compilers
• RISC-V Instruction Set Specifications
• RISC-V Compliance Test Suite

FAQ

• Why are components prefixed with Next*? - This is my second iteration of the core. Components that were rewritten were prefixed with Next. I liked the naming scheme and decided to keep it.

License

Copyright 2022 Nish Tahir

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.