Add Apple M1 Config on spir-v (#4)

-Adding tuned apple M1 Config for spirv kernels

Co-authored-by: nodlabs <nodlabs@mini0.local>

iree/compiler/Codegen/SPIRV/AppleConfig.cpp

@@ -0,0 +1,50 @@
+// Copyright 2021 The IREE Authors
+//
+// Licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+//===- AppleConfig.h - Apple CodeGen Configurations ---------------------===//
+//
+// This file contains CodeGen configurations for Apple M1 GPUs.
+//
+//===----------------------------------------------------------------------===//
+
+#include <array>
+
+#include "iree/compiler/Codegen/SPIRV/KernelConfig.h"
+#include "llvm/ADT/TypeSwitch.h"
+#include "mlir/Dialect/Linalg/IR/Linalg.h"
+#include "mlir/IR/BuiltinOps.h"
+
+namespace mlir {
+namespace iree_compiler {
+namespace detail {
+
+//===----------------------------------------------------------------------===//
+// Entry Point
+//===----------------------------------------------------------------------===//
+
+LogicalResult setAppleCodeGenConfig(const spirv::TargetEnv &targetEnv,
+                                     Operation *rootOp) {
+  int64_t subgroupSize = targetEnv.getResourceLimits().subgroup_size().getInt();
+  return TypeSwitch<Operation *, LogicalResult>(rootOp)
+      .Case<linalg::BatchMatmulOp, linalg::MatmulOp>([subgroupSize](auto op) {
+        std::array<int64_t, 2> workgroupXY = {256, 1};
+        std::array<int64_t, 3> threadMNK = {4, 4, 4};
+        return setMatmulOpConfig(op, subgroupSize, workgroupXY, threadMNK);
+      })
+      .Case<linalg::Conv2DNhwcHwcfOp>([subgroupSize](auto op) {
+        return setConvOpConfig(op, subgroupSize,
+                               /*bestTilingFactor=*/16);
+      })
+      .Case<linalg::DepthwiseConv2DNhwcHwcOp>([subgroupSize](auto op) {
+        return setConvOpConfig(op, subgroupSize,
+                               /*bestTilingFactor=*/16);
+      })
+      .Default([](Operation *) { return success(); });
+}
+
+}  // namespace detail
+}  // namespace iree_compiler
+}  // namespace mlir

iree/compiler/Codegen/SPIRV/BUILD

@@ -15,6 +15,7 @@ cc_library(
     srcs = [
         "AMDConfig.cpp",
         "AdrenoConfig.cpp",
+        "AppleConfig.cpp",
         "ConvertToSPIRVPass.cpp",
         "KernelConfig.cpp",
         "MaliConfig.cpp",

iree/compiler/Codegen/SPIRV/CMakeLists.txt

@@ -20,6 +20,7 @@ iree_cc_library(
   SRCS
     "AMDConfig.cpp"
     "AdrenoConfig.cpp"
+    "AppleConfig.cpp"
     "ConvertToSPIRVPass.cpp"
     "KernelConfig.cpp"
     "MaliConfig.cpp"

iree/compiler/Codegen/SPIRV/KernelConfig.cpp

@@ -541,6 +541,9 @@ static LogicalResult setSPIRVOpConfig(const spirv::TargetEnv &targetEnv,
     case spirv::Vendor::Qualcomm:
       result = detail::setAdrenoCodeGenConfig(targetEnv, rootOp);
       break;
+    case spirv::Vendor::Apple:
+      result = detail::setAppleCodeGenConfig(targetEnv, rootOp);
+      break;
     default:
       break;
   }

iree/compiler/Codegen/SPIRV/KernelConfig.h

@@ -52,6 +52,8 @@ LogicalResult setMatmulOpConfig(linalg::LinalgOp linalgOp, int64_t subgroupSize,
 
 LogicalResult setAdrenoCodeGenConfig(const spirv::TargetEnv &targetEnv,
                                      Operation *rootOp);
+LogicalResult setAppleCodeGenConfig(const spirv::TargetEnv &targetEnv,
+                                     Operation *rootOp);
 LogicalResult setAMDCodeGenConfig(const spirv::TargetEnv &targetEnv,
                                   Operation *rootOp);
 LogicalResult setMaliCodeGenConfig(const spirv::TargetEnv &targetEnv,