{"payload":{"pageCount":4,"repositories":[{"type":"Public","name":"chisel-nix","owner":"chipsalliance","isFork":false,"description":"Nix scripts used to manage the chisel projects.","allTopics":[],"primaryLanguage":{"name":"Nix","color":"#7e7eff"},"pullRequestCount":0,"issueCount":0,"starsCount":24,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-29T10:47:57.255Z"}},{"type":"Public","name":"rocket-uncore","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":2,"issueCount":0,"starsCount":6,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-29T10:17:57.523Z"}},{"type":"Public","name":"t1","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":22,"issueCount":17,"starsCount":112,"forksCount":21,"license":"Apache License 2.0","participation":[3,0,3,7,16,8,43,51,23,35,36,32,22,22,12,26,27,38,2,3,44,28,26,25,34,10,22,28,20,9,17,26,29,19,19,11,25,10,46,29,15,20,41,29,24,16,34,32,34,18,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-29T09:05:29.025Z"}},{"type":"Public","name":"sv-tests-results","owner":"chipsalliance","isFork":false,"description":"Output of the sv-tests runs.","allTopics":[],"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-29T03:07:00.634Z"}},{"type":"Public","name":"verible","owner":"chipsalliance","isFork":false,"description":"Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server","allTopics":["productivity","analysis","style-linter","language-server-protocol","syntax-tree","lexer","yacc","systemverilog","hacktoberfest","lsp-server","systemverilog-parser","systemverilog-developer","sv-lrm","verible","parser","formatter","linter"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":25,"issueCount":468,"starsCount":1332,"forksCount":202,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T21:00:20.936Z"}},{"type":"Public","name":"caliptra-sw","owner":"chipsalliance","isFork":false,"description":"Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":55,"issueCount":88,"starsCount":53,"forksCount":39,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T13:04:12.998Z"}},{"type":"Public","name":"chisel","owner":"chipsalliance","isFork":false,"description":"Chisel: A Modern Hardware Design Language","allTopics":["chip-generator","chisel","rtl","chisel3","firrtl","scala","verilog"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":155,"issueCount":306,"starsCount":3932,"forksCount":589,"license":"Apache License 2.0","participation":[10,7,13,8,6,8,9,2,19,18,5,8,0,6,12,17,21,21,7,11,16,21,9,6,4,6,6,12,11,4,7,11,2,12,7,9,5,10,9,9,21,9,11,7,12,13,7,7,5,43,2,13],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T11:05:33.332Z"}},{"type":"Public","name":"caliptra-rtl","owner":"chipsalliance","isFork":false,"description":"HW Design Collateral for Caliptra RoT IP","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":66,"starsCount":65,"forksCount":36,"license":"Apache License 2.0","participation":[16,5,11,11,29,9,16,12,9,11,13,1,2,4,3,13,3,0,0,1,2,3,1,5,3,3,4,5,1,3,4,1,2,0,1,1,3,1,3,8,0,0,0,0,1,0,1,2,1,2,2,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T03:42:16.405Z"}},{"type":"Public","name":"sv-tests","owner":"chipsalliance","isFork":false,"description":"Test suite designed to check compliance with the SystemVerilog standard.","allTopics":["rtl","verilog","systemverilog","hdl","compliance-testing","symbiflow"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":20,"issueCount":45,"starsCount":285,"forksCount":75,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T00:14:45.433Z"}},{"type":"Public","name":"Surelog","owner":"chipsalliance","isFork":false,"description":"SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX ","allTopics":["parser","linter","preprocessor","antlr","verilog","python-api","systemverilog","uvm","elaboration","vpi","antlr4-grammar","parser-ast","vpi-api","vpi-standard"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":48,"starsCount":357,"forksCount":68,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T22:25:40.707Z"}},{"type":"Public","name":"UHDM","owner":"chipsalliance","isFork":false,"description":"Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX","allTopics":["vpi-api","serialization","listener","systemverilog","ieee-standard","vpi-interface"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":15,"starsCount":192,"forksCount":39,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T22:20:21.412Z"}},{"type":"Public","name":"synlig-logs","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T15:30:41.885Z"}},{"type":"Public","name":"Cores-VeeR-EL2","owner":"chipsalliance","isFork":false,"description":"VeeR EL2 Core","allTopics":["fpga","processor","riscv","rtl","risc-v","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","el2"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":7,"issueCount":20,"starsCount":245,"forksCount":74,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T15:09:58.002Z"}},{"type":"Public","name":"synlig","owner":"chipsalliance","isFork":false,"description":"SystemVerilog support for Yosys","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":10,"issueCount":65,"starsCount":159,"forksCount":21,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T14:44:26.212Z"}},{"type":"Public","name":"Caliptra","owner":"chipsalliance","isFork":false,"description":"Caliptra IP and firmware for integrated Root of Trust block","allTopics":[],"primaryLanguage":null,"pullRequestCount":4,"issueCount":17,"starsCount":119,"forksCount":29,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-26T20:18:57.162Z"}},{"type":"Public","name":"caliptra-ss","owner":"chipsalliance","isFork":false,"description":"HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.","allTopics":["security","rot","ocp","root-of-trust","caliptra","opencomputeproject"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":2,"issueCount":11,"starsCount":3,"forksCount":2,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-25T22:55:11.285Z"}},{"type":"Public","name":"riscv-vector-tests","owner":"chipsalliance","isFork":false,"description":"Unit tests generator for RVV 1.0","allTopics":["generator","spike","riscv","testsuite","rvv"],"primaryLanguage":{"name":"Go","color":"#00ADD8"},"pullRequestCount":0,"issueCount":4,"starsCount":53,"forksCount":18,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-24T19:52:52.216Z"}},{"type":"Public","name":"aib-phy-hardware","owner":"chipsalliance","isFork":false,"description":"Advanced Interface Bus (AIB) die-to-die hardware open source","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":118,"forksCount":30,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-23T03:09:01.965Z"}},{"type":"Public","name":"i3c-core","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":1,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-19T07:30:32.513Z"}},{"type":"Public","name":"rocket-chip","owner":"chipsalliance","isFork":false,"description":"Rocket Chip Generator","allTopics":["chisel","scala","rocket-chip","chip-generator","riscv","rtl"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":61,"issueCount":227,"starsCount":3180,"forksCount":1119,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-17T23:50:33.490Z"}},{"type":"Public","name":"verilator","owner":"chipsalliance","isFork":true,"description":"Verilator open-source SystemVerilog simulator and lint system","allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":0,"starsCount":33,"forksCount":587,"license":"GNU Lesser General Public License v3.0","participation":[14,17,53,27,21,17,18,11,16,9,9,11,13,25,9,16,23,11,21,5,12,22,25,29,12,24,6,7,3,5,25,9,5,5,8,10,27,6,5,11,16,23,23,11,28,11,22,27,22,23,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-14T13:34:40.927Z"}},{"type":"Public","name":"firrtl-spec","owner":"chipsalliance","isFork":false,"description":"The specification for the FIRRTL language","allTopics":[],"primaryLanguage":{"name":"TeX","color":"#3D6117"},"pullRequestCount":17,"issueCount":23,"starsCount":39,"forksCount":27,"license":null,"participation":[0,0,0,0,5,18,22,0,1,5,4,0,0,0,3,0,3,1,21,5,8,1,5,0,3,4,1,1,4,1,1,0,0,3,0,1,0,0,4,0,1,2,1,1,3,5,1,2,0,3,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-13T21:04:39.748Z"}},{"type":"Public","name":"idealchisel","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-13T15:10:57.499Z"}},{"type":"Public","name":"caliptra-dpe","owner":"chipsalliance","isFork":false,"description":"High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":6,"issueCount":12,"starsCount":16,"forksCount":21,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T21:59:52.938Z"}},{"type":"Public","name":"dromajo","owner":"chipsalliance","isFork":false,"description":"RISC-V RV64GC emulator designed for RTL co-simulation","allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":6,"issueCount":18,"starsCount":210,"forksCount":63,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T23:41:08.578Z"}},{"type":"Public","name":"VeeR-EL2-Tock","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-09T11:24:44.595Z"}},{"type":"Public","name":"rvdecoderdb","owner":"chipsalliance","isFork":false,"description":"The Scala parser to parse riscv/riscv-opcodes generate","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":1,"issueCount":0,"starsCount":5,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-09T10:25:21.682Z"}},{"type":"Public","name":"firtool-resolver","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-06T19:39:45.646Z"}},{"type":"Public","name":"chips-alliance-website","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SCSS","color":"#c6538c"},"pullRequestCount":2,"issueCount":9,"starsCount":3,"forksCount":3,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-05T23:26:55.080Z"}},{"type":"Public","name":"tac","owner":"chipsalliance","isFork":false,"description":"CHIPS Alliance Technical Advisory Council","allTopics":[],"primaryLanguage":null,"pullRequestCount":1,"issueCount":19,"starsCount":5,"forksCount":22,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-05T23:24:15.207Z"}}],"repositoryCount":107,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"chipsalliance repositories"}